公开(公告)号：US09755052B2

公开(公告)日：2017-09-05

申请号：US14011078

申请日：2013-08-27

申请人： Yongping Ding ,  Sik Lui ,  Madhur Bobde ,  Lei Zhang ,  Jongoh Kim ,  John Chen

发明人： Yongping Ding ,  Sik Lui ,  Madhur Bobde ,  Lei Zhang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L21/265 ,  H01L29/739 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor power device disposed on a semiconductor substrate comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

公开(公告)号：US20170125514A9

公开(公告)日：2017-05-04

申请号：US14298922

申请日：2014-06-08

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/324 ,  H01L29/10

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

公开(公告)号：US09222196B2

公开(公告)日：2015-12-29

申请号：US13354014

申请日：2012-01-19

申请人： Steven L. Kimbel ,  Jihong (John) Chen ,  Richard G. Schrenker ,  Lee W. Ferry

发明人： Steven L. Kimbel ,  Jihong (John) Chen ,  Richard G. Schrenker ,  Lee W. Ferry

IPC分类号： C30B11/02 ,  C30B11/00 ,  C30B28/06 ,  C30B29/06

CPC分类号： C30B11/002 ,  C30B11/02 ,  C30B28/06 ,  C30B29/06 ,  Y10T117/1092

摘要： A directional solidification furnace includes a crucible for holding molten silicon and a lid covering the crucible and forming an enclosure over the molten silicon. The crucible also includes an inlet in the lid for introducing inert gas above the molten silicon to inhibit contamination of the molten silicon.

摘要翻译： 定向凝固炉包括用于保持熔融硅的坩埚和覆盖坩埚的盖，并在熔融硅上形成外壳。 坩埚还包括在盖子中的入口，用于在熔融硅上方引入惰性气体以抑制熔融硅的污染。

公开(公告)号：US20150115333A1

公开(公告)日：2015-04-30

申请号：US14062868

申请日：2013-10-24

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

IPC分类号： H01L29/10 ,  H01L29/808 ,  H01L27/06

CPC分类号： H01L29/1058 ,  H01L27/0727 ,  H01L29/0634 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

摘要翻译： 本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极和栅极之间形成的具有雪崩钳位二极管的超结结构。 横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

公开(公告)号：US20140175536A1

公开(公告)日：2014-06-26

申请号：US13724228

申请日：2012-12-21

申请人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

发明人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/28114 ,  H01L21/3081 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0292 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。 源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。 此外，有源器件可以具有两级栅极氧化物，其中栅极氧化物的下部具有大于栅极氧化物的上部的厚度T1的厚度T2。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20130299872A1

公开(公告)日：2013-11-14

申请号：US13911871

申请日：2013-06-06

申请人： HONG CHANG ,  JOHN CHEN

发明人： HONG CHANG ,  JOHN CHEN

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7393 ,  H01L27/0259 ,  H01L29/7827

摘要： A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 半导体器件包括设置在具有至少沟槽底部的多晶硅衬底的沟槽中的半导体材料。 半导体材料包括不同的掺杂区域，其被配置为在沟槽中形成的PNP或NPN结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08564055B2

公开(公告)日：2013-10-22

申请号：US13456406

申请日：2012-04-26

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US20130228860A1

公开(公告)日：2013-09-05

申请号：US13865941

申请日：2013-04-18

申请人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

发明人： Hong Chang ,  Yi Su ,  Wenjun Li ,  Limin Weng ,  Gary Chen ,  Jongoh Kim ,  John Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L21/283 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

公开(公告)号：US08519476B2

公开(公告)日：2013-08-27

申请号：US12643837

申请日：2009-12-21

申请人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/78 ,  H01L29/7811

摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

摘要翻译： 公开了自对准电荷平衡半导体器件及其形成方法。 在第一导电类型的半导体衬底上形成一个或多个平面栅极。 在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。 沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

公开(公告)号：US08252648B2

公开(公告)日：2012-08-28

申请号：US12826591

申请日：2010-06-29

申请人： Yeeheng Lee ,  Yongping Ding ,  John Chen

发明人： Yeeheng Lee ,  Yongping Ding ,  John Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782

摘要： A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

摘要翻译： 功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料 导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。 第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。 同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。