Fabrication of trench DMOS device having thick bottom shielding oxide
    1.
    发明授权
    Fabrication of trench DMOS device having thick bottom shielding oxide 有权
    具有厚底层屏蔽氧化物的沟槽DMOS器件的制造

    公开(公告)号:US09000514B2

    公开(公告)日:2015-04-07

    申请号:US13560247

    申请日:2012-07-27

    摘要: Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

    摘要翻译: 公开了半导体器件制造方法和器件。 可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分,使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻,以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。 或者,氧化物 - 氧化物 - 氧化物(ONO)结构可以形成在沟槽的侧壁和底部,并且可以在不被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

    Fabrication of trench DMOS device having thick bottom shielding oxide
    2.
    发明授权
    Fabrication of trench DMOS device having thick bottom shielding oxide 有权
    具有厚底层屏蔽氧化物的沟槽DMOS器件的制造

    公开(公告)号:US08252647B2

    公开(公告)日:2012-08-28

    申请号:US12551417

    申请日:2009-08-31

    IPC分类号: H01L21/336

    摘要: Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

    摘要翻译: 公开了半导体器件制造方法和器件。 可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分,使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻,以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。 或者,可以在沟槽的侧壁和底部形成氧化物 - 氧化物(ONO)结构,并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

    FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE
    3.
    发明申请
    FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE 有权
    具有厚度底层氧化物的TRENCH DMOS器件的制造

    公开(公告)号:US20110049618A1

    公开(公告)日:2011-03-03

    申请号:US12551417

    申请日:2009-08-31

    IPC分类号: H01L29/78 H01L21/336

    摘要: Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

    摘要翻译: 公开了半导体器件制造方法和器件。 可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分,使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻,以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。 或者,可以在沟槽的侧壁和底部形成氧化物 - 氧化物(ONO)结构,并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

    DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS
    4.
    发明申请
    DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS 有权
    直接与三层屏蔽门过程接触

    公开(公告)号:US20110068386A1

    公开(公告)日:2011-03-24

    申请号:US12565611

    申请日:2009-09-23

    IPC分类号: H01L29/78 H01L21/336

    摘要: A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

    摘要翻译: 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底,其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

    Direct contact in trench with three-mask shield gate process
    5.
    发明授权
    Direct contact in trench with three-mask shield gate process 有权
    直接接触沟槽与三屏蔽屏蔽门工艺

    公开(公告)号:US08847306B2

    公开(公告)日:2014-09-30

    申请号:US13343666

    申请日:2012-01-04

    摘要: A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译: 可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上方形成由绝缘体隔开的第二导电材料。 在沟槽上形成第一绝缘体层。 在衬底中形成体层。 源体形成在体层中。 在沟槽和源极上形成第二绝缘体层。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层上。 提供该摘要以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS
    6.
    发明申请
    DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS 有权
    直接与三层屏蔽门过程接触

    公开(公告)号:US20120098059A1

    公开(公告)日:2012-04-26

    申请号:US13343666

    申请日:2012-01-04

    IPC分类号: H01L21/28 H01L29/78

    摘要: A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译: 可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上方形成由绝缘体隔开的第二导电材料。 在沟槽上形成第一绝缘体层。 在衬底中形成体层。 源体形成在体层中。 在沟槽和源极上形成第二绝缘体层。 源极和栅极触点通过第二绝缘体层形成。 在第二绝缘体层上形成源极和栅极金属。 提供该摘要以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    Direct contact in trench with three-mask shield gate process
    7.
    发明授权
    Direct contact in trench with three-mask shield gate process 有权
    直接接触沟槽与三屏蔽屏蔽门工艺

    公开(公告)号:US08187939B2

    公开(公告)日:2012-05-29

    申请号:US12565611

    申请日:2009-09-23

    IPC分类号: H01L21/336 H01L29/66

    摘要: A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

    摘要翻译: 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底,其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

    Polysilicon control etch back indicator
    8.
    发明授权
    Polysilicon control etch back indicator 失效
    多晶硅控制回蚀指示器

    公开(公告)号:US08471368B2

    公开(公告)日:2013-06-25

    申请号:US13431551

    申请日:2012-03-27

    IPC分类号: H01L29/06

    摘要: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

    摘要翻译: 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器,其包括不同尺寸的沟槽,其具有填充在沟槽中的多晶硅,然后从更大的平面沟槽尺寸的一些沟槽中完全去除,并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

    Shallow source MOSFET
    9.
    发明授权
    Shallow source MOSFET 有权
    浅源MOSFET

    公开(公告)号:US07667264B2

    公开(公告)日:2010-02-23

    申请号:US10952231

    申请日:2004-09-27

    IPC分类号: H01L29/94

    摘要: A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

    摘要翻译: 半导体器件包括漏极,与漏极接触的主体,主体具有主体顶表面,嵌入在主体中的源,从主体顶表面向下延伸到主体中,延伸穿过源和主体的沟槽 并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模,在衬底中形成通过硬掩模的沟槽,在沟槽中沉积栅极材料,其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面,并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

    Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT)
    10.
    发明申请
    Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) 有权
    用于制造具有过多圆形屏蔽栅极沟槽(SGT)的MOSFET器件的工艺

    公开(公告)号:US20090148995A1

    公开(公告)日:2009-06-11

    申请号:US12378040

    申请日:2009-02-09

    IPC分类号: H01L21/336

    摘要: This invention discloses an improved method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) device. The method includes a step of opening a trench in substrate and covering trench walls of the trench with a linen layer followed by removing a portion of the linen layer from a bottom portion of the trench. The method further includes a step of opening a round hole by applying an isotropic substrate etch on the bottom portion of the trench with the round hole extending laterally from the trench walls. The method further includes a step of filling the trench and the round hole at the bottom of the trench with a gate material followed by applying a time etch to removed the gate material from a top portion of the trench whereby the gate material only filling the round hole up to a lateral expansion point of the round hole.

    摘要翻译: 本发明公开了一种用于制造沟槽金属氧化物半导体场效应晶体管(MOSFET)器件的改进方法。 该方法包括在衬底中打开沟槽并且用亚麻层覆盖沟槽的沟槽壁,然后从沟槽的底部去除一部分亚麻层的步骤。 该方法还包括通过在沟槽的底部施加各向同性的基底蚀刻来打开圆孔的步骤,其中圆形孔从沟槽壁横向延伸。 该方法还包括用栅极材料填充沟槽底部的沟槽和圆孔,然后施加时间蚀刻以从沟槽的顶部去除栅极材料的步骤,由此栅极材料仅填充圆形 孔直到圆孔的侧向膨胀点。