公开(公告)号：US08053287B2

公开(公告)日：2011-11-08

申请号：US11537265

申请日：2006-09-29

申请人： Tzu-Hsuan Hsu ,  Dun-Nian Yaung

发明人： Tzu-Hsuan Hsu ,  Dun-Nian Yaung

IPC分类号： H01L21/339

CPC分类号： H01L27/14645 ,  H01L27/1464

摘要： A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate to implant a second doped region over the first doped region. The combined thickness of the first and second doped region is greater than 50 percent of thickness of the substrate and the distance between back surface of the substrate and the first and second doped regions is less than 50 percent of thickness of the substrate. In this way, an enlarged light sensing region is formed through which electrons generated from back surface of the surface may easily reach the pixel.

摘要翻译： 提供制造背面照明传感器的方法。 提供衬底并且在衬底上执行高能离子注入以注入第一掺杂区域。 在衬底上形成层，并在衬底上执行自对准高能离子注入，以在第一掺杂区域上注入第二掺杂区域。 第一和第二掺杂区域的组合厚度大于衬底的厚度的50％，并且衬底的背表面与第一和第二掺杂区域之间的距离小于衬底厚度的50％。 以这种方式，形成放大的光感测区域，通过该放大的光感测区域从表面的后表面产生的电子可以容易地到达像素。

公开(公告)号：US08030721B2

公开(公告)日：2011-10-04

申请号：US12904903

申请日：2010-10-14

申请人： Tzu-Hsuan Hsu ,  Alex Hsu ,  Ching-Chun Wang

发明人： Tzu-Hsuan Hsu ,  Alex Hsu ,  Ching-Chun Wang

IPC分类号： H01L21/00

CPC分类号： H01L27/14689 ,  H01L21/26513 ,  H01L27/1463

摘要： Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.

摘要翻译： 提供一种制造图像传感器装置的方法，该图像传感器装置包括提供具有正面和背面的基板; 在衬底的前侧上形成光致抗蚀剂以限定具有第一宽度的开口，光致抗蚀剂具有与第一宽度相关的第一厚度; 通过使用与第一厚度相关的注入能量通过开口执行注入工艺，从而形成第一掺杂隔离特征; 形成与所述第一掺杂隔离特征相邻的光感测特征，所述光感测特征具有第二宽度; 以及从背面使衬底变薄，使得衬底具有不超过第一掺杂隔离特征深度的两倍的第二厚度。 像素尺寸基本上等于第一和第二宽度。

公开(公告)号：US08022466B2

公开(公告)日：2011-09-20

申请号：US11588830

申请日：2006-10-27

申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chih Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chih Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.

摘要翻译： 存储单元包括具有至少两个源极/漏极区域的半导体层，所述源极/漏极区域设置在半导体层的表面下方并被沟道区域分隔开; 设置在通道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 上部绝缘多层结构，其设置在所述电荷存储层上方，其中所述上部绝缘多层结构包括介于第一介电层和第二介电层之间的多晶硅材料层; 并且设置在上绝缘多层结构上方的栅极及其阵列及其操作方法。

公开(公告)号：US07939903B2

公开(公告)日：2011-05-10

申请号：US12651236

申请日：2009-12-31

申请人： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Ching-Chun Wang

发明人： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Ching-Chun Wang

IPC分类号： H01L31/00 ,  H01L31/062

CPC分类号： H01L27/14643 ,  H01L27/14625 ,  H01L27/1464

摘要： A backside-illuminated sensor including a semiconductor substrate. The semiconductor substrate has a front surface and a back surface. A plurality of pixels are formed on the front surface of the semiconductor substrate. At least one pixel includes a photogate structure. The photogate structure has a metal gate that includes a reflective layer.

摘要翻译： 背面照明传感器，包括半导体衬底。 半导体衬底具有前表面和后表面。 在半导体衬底的前表面上形成多个像素。 至少一个像素包括光栅结构。 光栅结构具有包括反射层的金属栅极。

公开(公告)号：US20110012192A1

公开(公告)日：2011-01-20

申请号：US12892044

申请日：2010-09-28

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

摘要翻译： 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。

公开(公告)号：US07851848B2

公开(公告)日：2010-12-14

申请号：US11756557

申请日：2007-05-31

申请人： Hang Ting Lue ,  Tzu Hsuan Hsu

发明人： Hang Ting Lue ,  Tzu Hsuan Hsu

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/0657 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/792 ,  H01L29/7926

摘要： A memory cell comprising: a source region and a drain region separated by a semiconductor channel region, the channel region having a channel surface having an area A1 including a first cylindrical region, a first dielectric structure on the channel surface, a dielectric charge trapping structure on the first dielectric structure, a second dielectric structure on the dielectric charge trapping structure, a conductive layer having a conductor surface having an area A2 including a second cylindrical region on the second dielectric structure, the conductor surface overlying the dielectric charge trapping structure and the channel surface of the channel region, and the ratio of the area A2 to the area A1 being greater than or equal to 1.2 are described along with devices thereof and methods for manufacturing.

摘要翻译： 一种存储单元，包括：由半导体沟道区分隔开的源极区和漏极区，所述沟道区具有沟道表面，该沟道表面具有包括第一圆柱形区域的区域A1，沟道表面上的第一介电结构，介电电荷俘获结构 在所述第一电介质结构上，在所述介电电荷俘获结构上的第二电介质结构，具有导体表面的导电层，所述导体表面具有包括所述第二电介质结构上的第二圆柱形区域的区域A2，所述导体表面覆盖所述介电电荷俘获结构和 通道区域的通道表面以及区域A2与区域A1的比率大于或等于1.2的描述与其装置及其制造方法一起被描述。

公开(公告)号：US20100290293A1

公开(公告)日：2010-11-18

申请号：US12845064

申请日：2010-07-28

申请人： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

发明人： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

摘要翻译： 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US07811890B2

公开(公告)日：2010-10-12

申请号：US11545575

申请日：2006-10-11

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

摘要翻译： 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。

公开(公告)号：US20100181638A1

公开(公告)日：2010-07-22

申请号：US12357094

申请日：2009-01-21

申请人： Ching-Chun Wang ,  Tzu-Hsuan Hsu

发明人： Ching-Chun Wang ,  Tzu-Hsuan Hsu

IPC分类号： H01L25/16 ,  H01L21/762

CPC分类号： H01L23/522 ,  H01L21/6836 ,  H01L21/76256 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.

摘要翻译： 提供一种制造半导体器件的方法，该半导体器件包括提供具有正面和背面的半导体衬底，在半导体衬底的正面形成第一电路和第二电路，将半导体衬底的正面粘合到 载体衬底，从背面减薄半导体衬底，并且从半导体衬底的背侧到前侧形成沟槽，以将第一电路与第二电路隔离。

公开(公告)号：US07495967B2

公开(公告)日：2009-02-24

申请号：US11601710

申请日：2006-11-20

申请人： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

发明人： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

摘要翻译： 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。