公开(公告)号：US07418689B2

公开(公告)日：2008-08-26

申请号：US10908102

申请日：2005-04-27

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US20080127018A1

公开(公告)日：2008-05-29

申请号：US11554637

申请日：2006-10-31

申请人： Charles J. Alpert ,  David J. Hathaway ,  William R. Migatz ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

发明人： Charles J. Alpert ,  David J. Hathaway ,  William R. Migatz ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

摘要翻译： 锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。 锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。 锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。 可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。 最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

公开(公告)号：US07225421B2

公开(公告)日：2007-05-29

申请号：US10905970

申请日：2005-01-28

申请人： William R. Migatz ,  Paul M. Campbell ,  David J. Hathaway ,  David S. Kung ,  Ruchir Puri ,  Louise H. Trevillyan

发明人： William R. Migatz ,  Paul M. Campbell ,  David J. Hathaway ,  David S. Kung ,  Ruchir Puri ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F1/10

摘要： A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

摘要翻译： 描述了一种方法，系统和程序产品，用于通过为集成电路中的一组时钟树叶元素中的每一个确定允许的布局区域来在集成电路上生成时钟分配网络。 通过确定和相交不同约束下的一组子区域来生成该允许的放置区域，每个子区域标识其中放置时钟树叶元素的区域以满足相应的约束。 确定子区域的约束包括松弛和拥挤约束形式的时间约束。 在确定了允许的放置区域之后，时钟树叶元素被聚集，并且每个时钟树叶元素被放置在其允许的放置区域内的位置，这使得该聚类的一些成本函数最小化。

公开(公告)号：US07178120B2

公开(公告)日：2007-02-13

申请号：US10338929

申请日：2003-01-08

申请人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

发明人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

IPC分类号： G06H17/50 ,  G06H9/45

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.

摘要翻译： 描述了在分布式环境中对VLSI芯片执行定时闭合的方法。 提取芯片的物理和定时资源并提供更新抽象的异步方法，可以同时优化芯片的多个分区。 将物理和时序资源的全局视图提供给同时实现时序收敛的局部优化。 层次结构的部分在单独的进程中进行了优化。 芯片的分区按照层次线执行，每个进程在层次结构中拥有单个分区。 这些过程可以由单个计算机执行，或者分布在本地网络中的多个计算机上。 虽然单个进程执行的优化仅适用于其给定的层次结构部分，但是在整个层次结构的上下文中进行决策。 这些优化包括放置，合成和路由。 本方法还可以扩展到包括路由资源，电源电流，功率/热预算，衬底噪声预算等其他资源，所有这些资源都能被类似地抽象和共享。

公开(公告)号：US06988255B2

公开(公告)日：2006-01-17

申请号：US10667083

申请日：2003-09-18

申请人： Robert J. Allen ,  Ravishankar Arunachalam ,  David J. Hathaway

发明人： Robert J. Allen ,  Ravishankar Arunachalam ,  David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.

公开(公告)号：US5535145A

公开(公告)日：1996-07-09

申请号：US383338

申请日：1995-02-03

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An abstracted delay model for a circuit network is generated wherein each internal node and connecting edges of an inputted detailed delay graph are processed. All delay edges in the delay graph which could contribute to an extreme delay path from some primary input of the delay graph are marked as necessary. Unnecessary edges are then removed to produce a partially abstracted delay graph. For each internal node in the partially abstracted delay graph, in-edges and out-edges of the node are then merged, if merging does not cause an increase in the number of edges in the delay graph, thus reducing the total number of edges in the delay abstraction.

摘要翻译： 生成电路网络的抽象延迟模型，其中处理输入的详细延迟图的每个内部节点和连接边缘。 延迟图中的所有可能有助于延迟图形的主要输入端的延迟路径的延迟边被标记为必要。 然后移除不必要的边以产生部分抽象的延迟图。 对于部分抽象的延迟图中的每个内部节点，节点的边缘和边缘然后合并，如果合并不会导致延迟图中边缘数量的增加，从而减少边缘总数 延迟抽象。

公开(公告)号：US5339253A

公开(公告)日：1994-08-16

申请号：US715178

申请日：1991-06-14

申请人： Keith M. Carrig ,  David J. Hathaway ,  Keith W. Lallier ,  Jeannie T. H. Panner ,  Terrence W. Sehr

发明人： Keith M. Carrig ,  David J. Hathaway ,  Keith W. Lallier ,  Jeannie T. H. Panner ,  Terrence W. Sehr

IPC分类号： G06F1/10 ,  G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5077 ,  G06F1/10

摘要： A signal distribution tree is constructed from the leaves to the root by pairing sinks having similar locations, latency requirements and generating function requirements, then determining the minimum cost route or routes between paired sinks, establishing at least one drive point for each minimum cost path which drive point will satisfy the latency requirements for the pair of sinks it serves and then treating each resulting set of drive points as a new sink to be paired while removing the initial sinks from the list of sinks to be paired, continuing this process iteratively until a single set of drive points results and, finally, connecting the signal source to one of the drive points in the final set.

摘要翻译： 通过配对具有相似位置，等待时间要求和生成功能需求的汇，然后确定配对接收器之间的最小成本路由或路由，为每个最小成本路径建立至少一个驱动点，从信号分配树构建信号分配树， 驱动点将满足其所服务的一对接收器的延迟要求，然后将每个所得到的驱动点集合作为待配对的新的接收器，同时从要配对的接收器列表中移除初始接收器，继续迭代过程直到 单个驱动点的结果，最后，将信号源连接到最终设置中的一个驱动点。

公开(公告)号：US4916627A

公开(公告)日：1990-04-10

申请号：US127323

申请日：1987-12-02

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

公开(公告)号：US3948423A

公开(公告)日：1976-04-06

申请号：US478861

申请日：1974-06-13

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： F41C33/00

CPC分类号： F41C33/002 ,  F41C33/001

摘要： An auxiliary gun sling, mountable to a rifle or shotgun, is utilized in combination with a conventional gun sling to securely hold a rifle or shotgun to the user's body when the weapon is not in use, and to facilitate a firm grip on the weapon as it is being fired. The sling is comprised of an elongated elastically extensible resilient strap having snap clips at either end for releasably mounting the strap to the front and back sling swivels of a rifle or shotgun. The auxiliary sling assures the user free use of both hands while carrying the weapon and facilitates quick and smooth movement of the weaponn from a carrying position to a firing position. At the firing position the tension of the resilient strap serves to hold the weapon firmly against the user's shoulder. The strap acts in conjunction with the conventional sling to firmly position the rifle barrel by bracing the user's rifle-supporting arm.

摘要翻译： 一个可以安装到步枪或霰弹枪上的辅助枪吊带与常规的枪支组合使用，以便在武器不使用时将步枪或霰弹枪牢固地固定在使用者的身上，并且有助于牢固地抓住武器。 它正在被解雇。 吊带由细长的弹性可伸展的弹性带组成，弹性带在任一端具有卡扣夹，用于可释放地将吊带安装在步枪或霰弹枪的前后吊索上。 辅助吊带确保使用者在携带武器时自由使用双手，并且便于将武器从携带位置快速平稳地移动到击发位置。 在发射位置，弹性带的张力用于将武器牢固地固定在用户的肩上。 绑带与常规吊带结合起来，通过支撑使用者的步枪支撑臂来牢固地定位步枪枪管。

公开(公告)号：US08776004B2

公开(公告)日：2014-07-08

申请号：US13006450

申请日：2011-01-14

申请人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

发明人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.

摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。