公开(公告)号：US06830850B1

公开(公告)日：2004-12-14

申请号：US09809901

申请日：2001-03-16

申请人： Zoran Krivokapic ,  Bhanwar Singh

发明人： Zoran Krivokapic ,  Bhanwar Singh

IPC分类号： G03H104

CPC分类号： G03F7/70216 ,  G03F7/001 ,  G03F7/70408 ,  G03H1/0005 ,  G03H1/0248 ,  G03H2001/0094 ,  G03H2001/0417 ,  G03H2260/14

摘要： An interferometric lithography method includes providing a first layer of material over a substrate and providing a second layer of material over the first layer of material. The method further includes providing a layer of photoresist over the first and second layers of material and providing coherent light to the first and second layers. The coherent light has an intensity insufficient to chemically transform the photoresist. The coherent light reflects off the first and layers to interfere with an intensity sufficient to chemically transform the photoresist.

摘要翻译： 干涉光刻方法包括在衬底上提供第一层材料，并在第一层材料上提供第二层材料。 该方法还包括在第一和第二层材料上提供一层光致抗蚀剂，并向第一层和第二层提供相干光。 相干光具有不足以化学转化光致抗蚀剂的强度。 相干光从第一层和第二层反射，以干涉足以使光刻胶化学转化的强度。

公开(公告)号：US06717212B2

公开(公告)日：2004-04-06

申请号：US09879724

申请日：2001-06-12

申请人： Dong-Hyuk Ju ,  William George En ,  Srinath Krishnan ,  Concetta E. Riccobene ,  Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

发明人： Dong-Hyuk Ju ,  William George En ,  Srinath Krishnan ,  Concetta E. Riccobene ,  Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

IPC分类号： H01L31392

CPC分类号： H01L21/76254 ,  H01L21/187 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78612

摘要： A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

摘要翻译： 一种用于制造绝缘体半导体（SOI）结构的装置和方法，其具有设置在半导体衬底和半导体层之间的具有泄漏的导热材料（LTCIM）层。

公开(公告)号：US06541821B1

公开(公告)日：2003-04-01

申请号：US09732952

申请日：2000-12-07

申请人： Srinath Krishnan ,  Witold P. Maszara ,  Zoran Krivokapic

发明人： Srinath Krishnan ,  Witold P. Maszara ,  Zoran Krivokapic

IPC分类号： H01L2972

CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

摘要： A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of its source and drain regions. The shallow pockets are of a conductivity type opposite to that of the source and drain regions and raise the threshold voltage of the transistor. The transistor also includes a deep pocket of dopants adjacent each of the source and drain regions to suppress the punch-through current.

摘要翻译： 绝缘体上硅绝缘体（SOI）晶体管包括在导电状态下完全耗尽的本征体层。 晶体管包括与其源极和漏极区域中的每一个相邻的掺杂物的浅阱。 浅槽口具有与源极和漏极区域相反的导电类型，并提高晶体管的阈值电压。 晶体管还包括与源极和漏极区域中的每一个相邻的掺杂剂的深口袋，以抑制穿通电流。

公开(公告)号：US06509234B1

公开(公告)日：2003-01-21

申请号：US10200652

申请日：2002-07-22

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66772

摘要： A method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes forming a T-shaped gate electrode formed at least in part in a recess formed in a layer of semiconductor material and over a body region that is disposed between a source and a drain. The method includes spacing the gate electrode from the body by a gate dielectric made from a high-K material.

摘要翻译： 一种形成完全耗尽的绝缘体上半导体（SOI）场效应晶体管（FET）的方法。 该方法包括形成至少部分地形成在半导体材料层中的凹部中的T形栅电极，以及设置在源极和漏极之间的体区。 该方法包括通过由高K材料制成的栅极电介质将栅电极与主体间隔开。

公开(公告)号：US06501135B1

公开(公告)日：2002-12-31

申请号：US09849669

申请日：2001-05-04

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L2701

CPC分类号： H01L29/66742 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78684

摘要： A germanium-on-insulator (GOI) device formed on a GOI structure with a buried oxide (BOX) layer disposed therein and an active layer disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The GOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions.

摘要翻译： 绝缘体上的锗绝缘体（GOI）器件形成在GOI结构上，其中埋置有氧化物（BOX）层，其中有源层设置在BOX层上，该有源层具有由隔离沟槽和BOX层限定的有源区。 GOI设备包括形成在活动区域​​之一上的门。 栅极限定插入在一个有源区域内形成的源极和漏极之间的沟道。

公开(公告)号：US06462381B1

公开(公告)日：2002-10-08

申请号：US09792146

申请日：2001-02-22

申请人： Stephen G. Beebe ,  Srinath Krishnan ,  Zoran Krivokapic

发明人： Stephen G. Beebe ,  Srinath Krishnan ,  Zoran Krivokapic

IPC分类号： H01L2362

CPC分类号： H01L23/60 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a filled backside contact opening disposed under and in thermal contact with at least one of the anode or the cathode, the backside contact opening traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

摘要翻译： 一种用于绝缘体上硅（SOI）集成电路的静电放电（ESD）保护装置，其具有设置在其上的掩埋氧化物层的硅衬底和设置在具有由隔离沟槽限定的有源区的掩埋氧化物层上的有源层。 所述ESD保护器件形成在所述SOI集成电路上并且具有形成在所述有源区域之一内并分别耦合到第一和第二节点的阳极和阴极; 以及设置在所述阳极或阴极中的至少一个之下并与其接触的填充的背面接触开口，所述背面接触开口穿过所述掩埋氧化物层以热耦合所述有源区域和所述衬底中的所述一个。

公开(公告)号：US06448161B1

公开(公告)日：2002-09-10

申请号：US09590877

申请日：2000-06-09

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L2122

CPC分类号： B82Y10/00 ,  H01L27/11 ,  H01L29/66772 ,  H01L29/882 ,  Y10S438/979

摘要： A method of forming a memory device from a single transistor and a single RTD structure is provided. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon layer has a first region and a second region. The second region is masked and a transistor device is formed in the first region of the top silicon layer. Next, the first region is masked and a vertical RTD device is formed in the second region. The step of forming a vertical RTD device in the second region comprises implanting a n+ dopant to form concurrently a source and drain region of the transistor device and a generally horizontal N+ quantum well region of the vertical RTD device. The drain region of the transistor device is coupled to the quantum well region of the vertical RTD. The N+ quantum well region is disposed horizontally below a top surface of the second region.

摘要翻译： 提供了从单个晶体管和单个RTD结构形成存储器件的方法。 该方法包括以下步骤：在基底上形成硅基底，氧化物层和氧化物层上的顶部薄硅层。 顶部硅层具有第一区域和第二区域。 第二区域被掩蔽，并且晶体管器件形成在顶部硅层的第一区域中。 接下来，第一区域被掩蔽，并且在第二区域中形成垂直的RTD器件。 在第二区域中形成垂直RTD器件的步骤包括注入n +掺杂剂以同时形成晶体管器件的源极和漏极区域以及垂直RTD器件的大致水平的N +量子阱区域。 晶体管器件的漏极区域耦合到垂直RTD的量子阱区域。 N +量子阱区域被设置在第二区域的顶表面之下。

公开(公告)号：US06396108B1

公开(公告)日：2002-05-28

申请号：US09711328

申请日：2000-11-13

申请人： Zoran Krivokapic ,  Matthew Buynoski

发明人： Zoran Krivokapic ,  Matthew Buynoski

IPC分类号： H01L21336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A self-aligned double gate transistor, comprising: a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region, and having a first side and a second side, the first side and the second side having a first gate oxide and a second gate oxide, respectively, formed thereon; a first silicon gate abutting said first side of said channel region on said insulator; and a second silicon gate abutting said second side of said channel on said insulator. A method for manufacturing a double gate transistor device, comprising: providing a substrate having a buried oxide region; depositing a first nitride mask layer having a pattern overlying a silicon region; forming a trench in said substrate with a depth to said buried oxide; forming a gate oxide in said trench; depositing polysilicon in said trench; depositing a second nitride mask layer having a pattern formed perpendicular to said first nitride mask; etching the portion of said polysilicon not underlying said first or second nitride layers; removing said second nitride layer; and implanting an impurity into exposed portions of polysilicon in said trench and of said silicon-on-insulator substrate underlying said second nitride layer.

摘要翻译： 一种自对准双栅极晶体管，包括：隔离层上的第一硅部分，所述硅部分中形成有源极区和由沟道区分离的漏极区，并且具有第一侧和第二侧， 并且第二侧分别具有形成在其上的第一栅极氧化物和第二栅极氧化物; 邻接所述绝缘体上的所述沟道区域的第一侧的第一硅栅极; 以及与所述绝缘体上的所述沟道的所述第二侧邻接的第二硅栅极。1.一种制造双栅极晶体管器件的方法，包括：提供具有掩埋氧化物区域的衬底; 沉积具有覆盖硅区域的图案的第一氮化物掩模层; 在所述衬底中形成具有所述掩埋氧化物的深度的沟槽; 在所述沟槽中形成栅极氧化物; 在所述沟槽中沉积多晶硅; 沉积具有垂直于所述第一氮化物掩模形成的图案的第二氮化物掩模层; 蚀刻所述多晶硅的不在所述第一或第二氮化物层下面的部分; 去除所述第二氮化物层; 以及将杂质注入所述沟槽中的多晶硅的暴露部分和所述第二氮化物层下面的所述绝缘体上硅衬底。

公开(公告)号：US06380589B1

公开(公告)日：2002-04-30

申请号：US09774138

申请日：2001-01-30

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L2701

CPC分类号： H01L27/11

摘要： A tunneling junction transistor (TJT) SRAM cell device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The SOI TJT SRAM cell device includes a first gate and a second gate stacked over one of the active regions. The first gate defines a channel interposed between a source and a drain formed within one of the active regions. The second gate includes a plurality of thin nitride layer interposed between an undoped region and the first gate electrode, a side gate electrode, and a polysilicon layer. The plurality of thin nitride layers form tunneling junctions between the electrodes. The SOI TJT SRAM cell device is electrically coupled respectively to a first and a second node; and a contact plug adjacent and in electrical contact with at least one of the source and the drain.

摘要翻译： 在绝缘体上半导体（SOI）衬底上形成有埋置氧化物（BOX）层的隧道结结晶体管（TJT）SRAM单元器件，以及设置在BOX层上的有源层，该有源层具有由隔离沟槽限定的有源区。 SOI TJT SRAM单元器件包括堆叠在一个有源区上的第一栅极和第二栅极。 第一栅极限定介于源极和漏极之间的通道，其形成在一个有源区域内。 第二栅极包括介于未掺杂区域和第一栅极电极，侧栅极电极和多晶硅层之间的多个薄氮化物层。 多个薄氮化物层在电极之间形成隧道结。 SOI TJT SRAM单元器件分别电耦合到第一和第二节点; 以及与源极和漏极中的至少一个相邻并与其接触的接触塞。

公开(公告)号：US06372563B1

公开(公告)日：2002-04-16

申请号：US09614894

申请日：2000-07-12

申请人： Zoran Krivokapic ,  Shekhar Pramanick

发明人： Zoran Krivokapic ,  Shekhar Pramanick

IPC分类号： H01L2100

CPC分类号： H01L21/28052 ,  H01L21/2022 ,  H01L21/28097 ,  H01L21/28123 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66651

摘要： A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

摘要翻译： 具有体接触和硅化物栅的自对准SOI器件。 SOI器件使用诸如硅的普通衬底形成。 硅化物栅极是自对准的，并由镍和非晶硅的再结晶形成。 自对准硅化物栅极包括栅极接触区域，并且相对于栅极开口，源极和漏极区域以及氮化物隔离层自对准。 沉积在隔离层附近的镍间隔物和沉积在镍间隔物之间​​的非晶硅通过硅化工艺形成自对准的硅化物栅极。