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71.发明申请STORING A TARGET ADDRESS OF A CONTROL TRANSFER INSTRUCTION IN AN INSTRUCTION FIELD 审中-公开在指挥领域存储控制传输指令的目标地址公开(公告)号：US20130138888A1
公开(公告)日：2013-05-30
申请号：US13307850
申请日：2011-11-30
IPC分类号： G06F12/08
CPC分类号： G06F9/324 , G06F9/382 , G06F12/0862 , Y02D10/13
摘要： A control transfer instruction (CTI), such as a branch, jump, etc., may have an offset value for a control transfer that is to be performed. The offset value may be usable to compute a target address for the CTI (e.g., the address of a next instruction to be executed for a thread or instruction stream). The offset may be specified relative to a program counter. In response to detecting a specified offset value, the CTI may be modified to include at least a portion of a computed target address. Information indicating this modification has been performed may be stored, for example, in a pre-decode bit. In some cases, CTI modification may be performed only when a target address is a “near” target, rather than a “far” target. Modifying CTIs as described herein may eliminate redundant address calculations and produce a savings of power and/or time in some embodiments.
摘要翻译： 诸如分支，跳转等的控制传送指令（CTI）可以具有要执行的控制传输的偏移值。 偏移值可用于计算CTI的目标地址（例如，针对线程或指令流执行的下一条指令的地址）。 可以相对于程序计数器指定偏移量。 响应于检测到指定的偏移值，可以修改CTI以包括计算的目标地址的至少一部分。 已经执行了表示该修改的信息可以被存储在例如预解码位中。 在某些情况下，仅当目标地址是“近”目标而不是“远”目标时才可以执行CTI修改。 如本文所述的修改CTI可以在一些实施例中消除冗余地址计算并产生功率和/或时间的节省。
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公开(公告)号：US08358780B2
公开(公告)日：2013-01-22
申请号：US13291026
申请日：2011-11-07
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： Described is an execution unit for performing at least part of the Data Encryption Standard that includes a Left Half input; a Key input; and a Table input, as well as a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output that is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 描述了用于执行包括左半输入的数据加密标准的至少一部分的执行单元; 一键输入 和Table输入，以及被配置为接收Table输入的第一组晶体管，执行表查找和输出数据。 执行单元还包括具有两个输入的第一异或运算符和被配置为接收左半输入和键输入的输出。 执行单元还包括具有两个输入的第二异或运算符和被配置为接收由第一组晶体管输出的数据并且接收第一个异或运算符的输出的输出。 执行单元还包括具有两个输入的第三异或运算符和被配置为接收左半输入和由第一组晶体管输出的数据的输出。
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73.发明申请SUPPRESSION OF CONTROL TRANSFER INSTRUCTIONS ON INCORRECT SPECULATIVE EXECUTION PATHS 有权禁止不正当执行执行机构的控制转移指令公开(公告)号：US20120290820A1
公开(公告)日：2012-11-15
申请号：US13228329
申请日：2011-09-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3842 , G06F9/3844 , G06F9/3861
摘要： Techniques are disclosed relating to a processor that is configured to execute control transfer instructions (CTIs). In some embodiments, the processor includes a mechanism that suppresses results of mispredicted younger CTIs on a speculative execution path. This mechanism permits the branch predictor to maintain its fidelity, and eliminates spurious flushes of the pipeline. In one embodiment, a misprediction bit is be used to indicate that a misprediction has occurred, and younger CTIs than the CTI that was mispredicted are suppressed. In some embodiments, the processor may be configured to execute instruction streams from multiple threads. Each thread may include a misprediction indication. CTIs in each thread may execute in program order with respect to other CTIs of the thread, while instructions other than CTIs may execute out of program order.
摘要翻译： 公开了涉及被配置为执行控制传送指令（CTI）的处理器的技术。 在一些实施例中，处理器包括抑制推测性执行路径上的错误的较新CTI的结果的机制。 这种机制允许分支预测器保持其保真度，并且消除管道的杂散冲洗。 在一个实施例中，错误预测位用于指示发生了错误预测，并且抑制了比错误预测的CTI更年轻的CTI。 在一些实施例中，处理器可以被配置为执行来自多个线程的指令流。 每个线程可以包括错误预测指示。 每个线程中的CTI可以以相对于线程的其他CTI的程序顺序执行，而除了CTI之外的指令可以执行程序顺序。
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公开(公告)号：US20120290817A1
公开(公告)日：2012-11-15
申请号：US13228347
申请日：2011-09-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and a tag may indicate the location of the stored target. The tag may be associated with the CTI rather than associating the complete target address with the CTI. When the CTI reaches an execution stage of the processor, the tag may be used to retrieve the predicted target address. In some embodiments using a tag to retrieve a predicted target, CTI instructions from different processor threads may be interleaved without affecting retrieval of predicted targets.
摘要翻译： 处理器，被配置为便于传送和存储用于控制传输指令（CTI）的预测目标。 在某些实施例中，处理器可以是多线程的并且支持对多个线程的预测目标的存储。 在一些实施例中，CTI分支目标可以由处理器的一个元件存储，并且标签可以指示所存储的目标的位置。 标签可能与CTI相关联，而不是将完整的目标地址与CTI相关联。 当CTI到达处理器的执行阶段时，该标签可用于检索预测的目标地址。 在使用标签检索预测目标的一些实施例中，来自不同处理器线程的CTI指令可以被交错而不影响预测目标的检索。
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公开(公告)号：US20120216020A1
公开(公告)日：2012-08-23
申请号：US13031571
申请日：2011-02-21
IPC分类号： G06F9/30
CPC分类号： G06F9/30014 , G06F9/30029 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3889 , G06F21/71 , G06F21/72 , H04L9/065 , H04L63/0457
摘要： Techniques relating to a processor that provides instruction-level support for a stream cipher are disclosed. In one embodiment, the processor supports a first instruction executable to perform an alpha multiplication, an alpha division, and an exclusive-OR operation using a result of the alpha multiplication and a result of the alpha division. In one embodiment, the processor supports a second instruction executable to perform a modular addition of a value R1 and a value S, and to perform a first exclusive-OR operation on a result of the modular addition and a value R2. In one embodiment, the processor supports a third instruction executable to perform a substitution-box (S-Box) operation on a value R1 to produce a value R2′, and to perform a modular addition using a value R2 to produce a value R1'.
摘要翻译： 公开了与为流密码提供指令级支持的处理器有关的技术。 在一个实施例中，处理器支持可执行第一指令以使用α乘法的结果和α分割的结果执行α乘法，α分割和异或运算。 在一个实施例中，处理器支持可执行第二指令以执行值R1和值S的模块化添加，并且对模块化加法的结果和值R2执行第一异或运算。 在一个实施例中，处理器支持可执行第三指令以对值R1执行替代（S-Box）操作以产生值R2'，并且使用值R2执行模数相加以产生值R1' 。
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76.发明申请公开(公告)号：US20120060057A1
公开(公告)日：2012-03-08
申请号：US13295554
申请日：2011-11-14
IPC分类号： G06F11/14
CPC分类号： G06F11/10
摘要： In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
摘要翻译： 在一个实施例中，处理器包括被配置为存储推测寄存器状态的第一寄存器文件，被配置为存储提交寄存器状态的第二寄存器文件，检查电路和控制单元。 第一个寄存器文件由第一个错误保护方案保护，第二个寄存器文件由第二个错误保护方案保护。 耦合检查电路以响应于处理器选择要提交的第一指令，接收从第一寄存器文件读取的值和对应的一个或多个校验位以提交给第二寄存器堆。 检查电路被配置为响应于该值和校验位来检测该值中的错误。 耦合到检查电路，控制单元被配置为响应于由检查电路检测到的错误而引起第一指令的再次执行。
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公开(公告)号：US08073141B2
公开(公告)日：2011-12-06
申请号：US12200792
申请日：2008-08-28
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译： 适于执行数据加密标准的至少一部分的执行单元。 执行单元包括左半输入; 一键输入 和一个表输入。 执行单元还包括被配置为接收表输入，执行表查找和输出数据的第一组晶体管。 执行单元还包括具有两个输入和一个输出的第一个异或运算符。 第一个独占或运算符被配置为接收左半输入和键输入。 执行单元还包括具有两个输入和一个输出的第二个异或运算符。 第二异或运算符被配置为接收由第一组晶体管输出的数据并且接收第一异或运算符的输出。 执行单元还包括具有两个输入和一个输出的第三个异或运算符。 第三个异或运算符被配置为接收第一组晶体管的左半输入和数据输出。
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78.发明申请APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR PERFORMING A CYCLIC REDUNDANCY CHECK (CRC) 有权实施循环冗余检查（CRC）的指导性支持的装置和方法公开(公告)号：US20110231636A1
公开(公告)日：2011-09-22
申请号：US12725243
申请日：2010-03-16
CPC分类号： G06F9/3861 , G06F9/30007 , G06F9/30018 , G06F9/3851 , G06F9/3885 , G06F11/1004 , G06F21/72 , H03M13/09 , H03M13/096 , H03M13/158 , H04L1/0041 , H04L1/0061 , H04L9/0631
摘要： Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41. In some embodiments, the first instance of the CRC instruction specifies an initial value to be used in performing the first CRC operation, the set of data, and a storage location in which the cryptographic unit is configured to store the checksum value produced by the first CRC operation.
摘要翻译： 涉及包括执行循环冗余校验（CRC）操作的指令支持的处理器的技术。 处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。 处理器可以包括被配置为接收包括在ISA内定义的循环冗余校验（CRC）指令的第一实例的指令的加密单元，其中CRC指令的第一实例可由密码单元执行以执行第一CRC操作 在产生校验和值的一组数据上。 在一个实施例中，密码单元被配置为使用生成器多项式0x11EDC6F41生成校验和值。 在一些实施例中，CRC指令的第一实例指定用于执行第一CRC操作，数据集合和存储位置的初始值，其中密码单元被配置为存储由第一个CRC操作产生的校验和值 CRC操作。
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79.发明申请公开(公告)号：US20110087895A1
公开(公告)日：2011-04-14
申请号：US12575832
申请日：2009-10-08
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/3826 , G06F9/3873 , G06F21/72 , H04L9/0637 , H04L2209/12 , H04L2209/125 , H04L2209/24
摘要： A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.
摘要翻译： 处理器可以包括被配置为发出用于执行的指令的硬件指令获取单元和被配置为接收用于执行的指令的硬件功能单元，其中所述指令包括加密指令和非加密指令。 功能单元可以包括被配置为执行具有相应的加密执行等待时间的加密指令的密码执行流水线，以及配置成执行非加密指令的非加密执行流水线，该非加密执行流水线的长度大于 加密执行延迟。 功能单元还可以包括局部旁路网络，其被配置为将由密码执行流水线产生的结果旁路到在密码执行流水线内执行的依赖密码指令，使得依赖密码指令序列内的每个指令都可以用密码执行等待时间执行， 并且其中加密执行流水线的结果不被旁路到处理器内的任何其他功能单元。
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80.发明申请MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSORS EMPLOYING REGISTER WINDOWS 有权多用途处理器和使用注册窗口的处理器的多个寄存器文件公开(公告)号：US20110078414A1
公开(公告)日：2011-03-31
申请号：US12570682
申请日：2009-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30127 , G06F9/3013 , G06F9/30141 , G06F9/3851 , G11C8/16
摘要： A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.
摘要翻译： 处理器包括：指令获取单元，被配置为发出用于执行的指令，其中从多个线程中选择指令，其中每个给定指令具有对应的线程标识符，并且其中至少一些指令经由寄存器指定操作数 身份标识。 寄存器文件存储指令可用的操作数，并且可以包括几个存储体，每个存储体对应于寄存器标识符，并且包括与多个线程对应的多个条目，其中条目被配置为存储数据值。 响应于接收到针对给定线程标识符读取特定寄存器标识符的请求，寄存器文件可以被配置为对给定的线程标识符进行解码以从对应于给定线程标识符的存储体检索条目。 寄存器文件还可以从检索到的条目中选择与要输出的特定寄存器标识符对应的数据值。
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