公开(公告)号：US06844580B2

公开(公告)日：2005-01-18

申请号：US10361710

申请日：2003-02-11

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L27/146 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14601 ,  H01L27/14636

摘要： An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

摘要翻译： 形成为CMOS半导体集成电路的成像装置包括在浮动扩散区域和源极跟随器输出晶体管的栅极之间的埋置接触线。 CMOS成像器中的自对准埋入触点减少了从扩散区到衬底的泄漏，这可能与用于将扩散区与源极跟随器晶体管栅互连的其它技术发生。 此外，在浮动扩散区域和源极跟随器晶体管栅极之间最佳地形成自对准埋入触点，其允许源极跟随器晶体管放置得更靠近浮动扩散区域，从而允许在相同尺寸的成像器中的较大光电检测区域 电路。

公开(公告)号：US06821852B2

公开(公告)日：2004-11-23

申请号：US09782743

申请日：2001-02-13

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L218234

CPC分类号： H01L21/823892 ,  H01L21/2652 ,  H01L21/823842

摘要： A method of forming an integrated circuit dual gate structure using only one mask is disclosed. In one embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having an NWELL is formed without using a mask, and a second gate structure having a PWELL is formed using only one mask. In an alternate embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having a PWELL is formed without using a mask, and a second gate structure having an NWELL is formed using only one mask.

摘要翻译： 公开了仅使用一个掩模形成集成电路双栅极结构的方法。 在一个实施例中，制备用于制造双栅极结构的衬底，在不使用掩模的情况下形成具有NWELL的第一栅极结构，并且仅使用一个掩模形成具有PWELL的第二栅极结构。 在替代实施例中，准备用于制造双栅极结构的衬底，在不使用掩模的情况下形成具有PWELL的第一栅极结构，并且仅使用一个掩模形成具有NWELL的第二栅极结构。

公开(公告)号：US06756616B2

公开(公告)日：2004-06-29

申请号：US09941546

申请日：2001-08-30

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L31062

CPC分类号： H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14645

摘要： A CMOS imager having multiple graded doped regions formed below respective pixel sensor cells is disclosed. A deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response.

摘要翻译： 公开了一种CMOS成像器，其具有形成在相应的像素传感器单元下方的多个渐变掺杂区域。 在半导体衬底的红色像素传感器单元下方形成深逆转p阱以增加红色响应。 在蓝色像素传感器单元下方形成浅的p阱，以减少红色和绿色响应，而在绿色像素传感器单元下方形成浅逆行p阱以增加绿色响应并降低红色响应。

公开(公告)号：US06740915B1

公开(公告)日：2004-05-25

申请号：US09190055

申请日：1998-11-12

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L2714

CPC分类号： H01L21/823406 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

摘要： An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact between the floating diffusion region and the gate of a source follower output transistor. The buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a buried contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

摘要翻译： 形成为CMOS半导体集成电路的成像装置包括浮动扩散区域和源极跟随器输出晶体管的栅极之间的埋入接触。 CMOS成像器中的埋入触点减少了从扩散区域到衬底的泄漏，这可能与用于使扩散区域与源极跟随器晶体管栅极互连的其它技术发生。 此外，具有在浮动扩散区域和源极跟随器晶体管栅极之间的埋置接触的CMOS成像器允许源极跟随器晶体管被放置得更靠近浮动扩散区域，由此允许在相同尺寸的成像器电路中的较大的光检测区域。

公开(公告)号：US06645788B2

公开(公告)日：2003-11-11

申请号：US10073136

申请日：2002-02-13

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L2100

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14687 ,  H01L31/035236 ,  H01L31/113

摘要： A CMOS imager having an epitaxial layer formed below pixel sensor cells is disclosed. An epitaxial layer is formed between a semiconductor substrate and a photosensitive region to improve the cross-talk between pixel cells. The thickness of the epitaxial layer is optimized so that the collection of signal carriers by the photosensitive region is maximized.

公开(公告)号：US06639261B2

公开(公告)日：2003-10-28

申请号：US09207593

申请日：1998-12-08

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L31101

CPC分类号： H01L27/14636 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/335

摘要： An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

摘要翻译： 形成为CMOS半导体集成电路的成像装置包括在浮动扩散区域和源极跟随器输出晶体管的栅极之间的掺杂多晶硅接触线。 CMOS成像器中的掺杂多晶硅接触线减少了从扩散区到衬底的泄漏，这可能与用于使扩散区与源极跟随器晶体管栅相互连接的其它技术发生。 此外，在浮动扩散区域和源极跟随器晶体管栅极之间具有掺杂多晶硅接触的CMOS成像器允许源极跟随器晶体管被放置得更靠近浮动扩散区域，从而允许在相同尺寸的成像器电路中的更大的光检测区域。

公开(公告)号：US06630701B1

公开(公告)日：2003-10-07

申请号：US09374988

申请日：1999-08-16

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L31062

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

摘要： A buried channel CMOS imager having an improved signal to noise ratio is disclosed. The buried channel CMOS imager provides reduced noise by keeping collected charge away from the surface of the substrate, thereby improving charge loss to the substrate. The buried channel CMOS imager thus exhibits a better signal-to-noise ratio. Also disclosed are processes for forming the buried channel CMOS imager.

摘要翻译： 公开了具有改善的信噪比的掩埋通道CMOS成像器。 掩埋沟道CMOS成像器通过将收集的电荷远离衬底的表面提供降低的噪声，从而改善对衬底的电荷损失。 掩埋通道CMOS成像器因此表现出更好的信噪比。 还公开了用于形成掩埋沟道CMOS成像器的工艺。

公开(公告)号：US06611013B2

公开(公告)日：2003-08-26

申请号：US09777890

申请日：2001-02-07

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L31062

CPC分类号： H01L27/1462 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689

摘要： The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

摘要翻译： 本发明还涉及一种用于选择性地在CMOS成像器的晶体管栅极上提供硅化物涂层以提高晶体管栅极的速度的装置和方法。 该方法还包括用于在CMOS成像器上形成自对准照相屏蔽的装置和方法。

公开(公告)号：US06500692B1

公开(公告)日：2002-12-31

申请号：US09782060

申请日：2001-02-14

申请人： Howard E. Rhodes

发明人： Howard E. Rhodes

IPC分类号： H01L2100

CPC分类号： H01L27/14689 ,  H01L27/14603 ,  H01L27/14643

摘要： A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.

摘要翻译： 一种用于具有改进的充电容量的CMOS成像器中的沟道光电传感器。 沟道光电传感器可以是光栅或光电二极管结构。 光电传感器的沟槽形状与在基片上占据可比区域的平面光电传感器相比，提供了增加的表面积。 沟道光电传感器还具有更高的充电容量，改善的动态范围和更好的信噪比。 还公开了用于形成沟槽光电传感器的工艺。

公开(公告)号：US06445014B1

公开(公告)日：2002-09-03

申请号：US09645582

申请日：2000-08-25

申请人： Howard E. Rhodes ,  Mark Durcan

发明人： Howard E. Rhodes ,  Mark Durcan

IPC分类号： H01L31062

CPC分类号： H01L27/14601 ,  H01L27/14609

摘要： A retrograde and periphery well structure for a CMOS imager is disclosed which improves the quantum efficiency and signal-to-noise ratio of the photosensing portion imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. The periphery well contains peripheral logic circuitry for the imager. By providing retrograde and peripheral wells, circuitry in each can be optimized. Also disclosed are methods for forming the retrograde and peripheral well.

摘要翻译： 公开了用于CMOS成像器的逆行和外围阱结构，其提高了光敏部分成像器的量子效率和信噪比。 逆行阱包括具有垂直梯度掺杂剂浓度的掺杂区域，其在衬底表面处最低，并且在阱的底部最高。 单个逆行井可以具有单个像素传感器单元，多个像素传感器单元，或甚至其中形成的像素传感器单元的整个阵列。 逆行阱底部的高度集中的区域驱使来自光电传感器的信号载体，使得它们不会损失到衬底上，并且防止来自衬底的噪声载流子向上扩散到光电传感器中。 外围井包含成像器的外围逻辑电路。 通过提供逆行和外围井，可以优化每个电路。 还公开了形成逆行和外周井的方法。