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    Large area, fast frame rate charge coupled device
    2.
    发明申请
    Large area, fast frame rate charge coupled device 失效

    公开(公告)号：US20040033656A1

    公开(公告)日：2004-02-19

    申请号：US10641640

    申请日：2003-08-14

    申请人： Fairchild Imaging

    发明人： David Wen ,  Steve Onishi

    IPC分类号： H01L021/8238

    CPC分类号： H01L21/823406 ,  H01L27/14687 ,  H01L27/14843

    摘要： Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

    Solid-state imaging device and method of manufacturing the same
    5.
    发明授权
    Solid-state imaging device and method of manufacturing the same 失效
    固态成像装置及其制造方法

    公开(公告)号：US5286669A

    公开(公告)日：1994-02-15

    申请号：US887662

    申请日：1992-05-26

    申请人： Toru Maeda ,  Patsuzo Kawaguchi

    发明人： Toru Maeda ,  Patsuzo Kawaguchi

    IPC分类号： H01L21/8234 ,  H01L27/148 ,  H01L21/339

    CPC分类号： H01L27/148 ,  H01L21/823406

    摘要： The invention relates to a solid-state imaging device in which a light-sensitive element region and a charge transfer region are separately formed on a semiconductor substrate of a first conductivity type by implanting an impurity of a second conductivity type into the substrate. A channel region is formed between these two regions by implanting an impurity of the first conductivity type into the substrate. Next, charge transfer electrodes made of a light-proof material are formed on the light-sensitive element region and the charge transfer region, with insulating films thereunder.An alloy of a high-melting-point metal and silicon is used in the construction of the charge transfer electrodes, and this alloy is subjected to high-temperature processing in an atmosphere of O.sub.2.

    摘要翻译： 本发明涉及一种固态成像装置，其中通过将第二导电类型的杂质注入衬底中，在第一导电类型的半导体衬底上分别形成光敏元件区域和电荷转移区域。 通过将第一导电类型的杂质注入衬底中，在这两个区域之间形成沟道区。 接下来，在感光元件区域和电荷转移区域上形成由耐光材料制成的电荷转移电极，其下具有绝缘膜。 在电荷转移电极的构造中使用高熔点金属和硅的合金，并且将该合金在O 2气氛中进行高温处理。

    Co-planar barrier-type charge coupled device with enhanced storage capacity and decreased leakage current
    6.
    发明授权
    Co-planar barrier-type charge coupled device with enhanced storage capacity and decreased leakage current 失效
    共平面势垒型电荷耦合器件具有增强的存储容量和降低的漏电流

    公开(公告)号：US4365261A

    公开(公告)日：1982-12-21

    申请号：US828079

    申请日：1977-08-26

    申请人： Pallab K. Chatterjee ,  Aloysious F. Tasch, Jr.

    发明人： Pallab K. Chatterjee ,  Aloysious F. Tasch, Jr.

    IPC分类号： G11C27/04 ,  G11C19/28 ,  H01L21/339 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/762 ,  H01L29/768 ,  H01L29/78 ,  G11C11/34

    CPC分类号： H01L29/66954 ,  G11C19/287 ,  H01L21/823406 ,  H01L27/1057 ,  H01L29/76875

    摘要： A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. An insulating layer of uniform thickness lies on the first surface. A charge transfer channel extends through each stage. Phase electrodes lie on the insulating layer transversely to the channel. The semiconductor substrate under each phase electrode is divided into a barrier region and an adjacent well region bounded by the channel. A shallow dopant layer of the first-type conductivity lies in each of the barrier regions relatively near to the first surface. A buried channel dopant layer of a second-type conductivity lies in the well regions and the barrier regions under and relatively near to the shallow first-type conductivity dopant layer. Additionally, an enhanced first-type conductivity dopant layer lies in the well regions and the barrier regions under and relatively near to the buried channel dopant layer of second-type conductivity.

    摘要翻译： 公开了一种电荷耦合器件，其包括具有增加的电荷存储容量和减小的漏电流的多个级。 每个级由具有第一表面的第一类型导电性半导体衬底组成。 均匀厚度的绝缘层位于第一表面上。 电荷转移通道延伸穿过每个阶段。 相位电极位于绝缘层上横向于通道。 各相电极下的半导体基板被分割为由通道界定的阻挡区域和相邻的阱区域。 第一类型导电性的浅掺杂剂层位于相对靠近第一表面的每个屏障区域中。 第二类导电性的掩埋沟道掺杂剂层位于阱区和位于浅第一类型导电掺杂剂层之下且相对靠近浅第一类型导电掺杂剂层的势垒区域。 此外，增强的第一类型导电性掺杂剂层位于第二导电性的掩埋沟道掺杂剂层下方的阱区域和势垒区域，并且相对靠近第二类型导电性的掩埋沟道掺杂剂层。

    Method of making buried channel charge coupled device with means for controlling excess charge
    7.
    发明授权
    Method of making buried channel charge coupled device with means for controlling excess charge 失效
    用于控制过量电荷的装置的掩埋通道电荷耦合器件的方法

    公开(公告)号：US4362575A

    公开(公告)日：1982-12-07

    申请号：US297055

    申请日：1981-08-27

    申请人： Lloyd F. Wallace

    发明人： Lloyd F. Wallace

    IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/339 ,  H01L21/8234 ,  H01L27/14 ,  H01L27/148 ,  H01L29/762 ,  H04N5/30 ,  H04N5/372 ,  H01L27/10 ,  H01L21/263

    CPC分类号： H01L21/823406 ,  H01L21/033 ,  H01L21/266 ,  H01L27/14887

    摘要： The preferred embodiment of a method of making a buried channel CCD starts with a body of P type semiconductor material over which an oxide layer and a photoresist are deposited. Openings are formed to expose regions of the body surface where drains are to be formed and N type impurity atoms are implanted through the openings. The openings are then enlarged to expose an additional area of the surface surrounding the drains and P type atoms are implanted through the enlarged openings to form channel stops. Afterward, the surface of the body is exposed and N type atoms are implanted to form buried channel regions on each side of the channel stops and to convert a thin layer of the channel stops to lightly doped compensation regions extending between the drains and the buried channel regions.

    摘要翻译： 制造掩埋沟道CCD的方法的优选实施例从P型半导体材料体开始，在其上沉积氧化物层和光致抗蚀剂。 形成开口以暴露将要形成排水沟的体表面的区域，并且通过开口注入N型杂质原子。 然后扩大开口以暴露出围绕排水沟的表面的附加区域，并通过扩大的开口植入P型原子以形成通道停止。 之后，暴露体表面，注入N型原子，形成通道每侧的掩埋沟道区域，并将通道的薄层转换为在漏极和埋入通道之间延伸的轻掺杂补偿区域 地区。

    Process for making a dual implanted drain extension for bucket brigade device tetrode structure
    8.
    发明授权
    Process for making a dual implanted drain extension for bucket brigade device tetrode structure 失效
    用于铲斗装备四级结构的双注入漏极延伸的工艺

    公开(公告)号：US4358890A

    公开(公告)日：1982-11-16

    申请号：US293903

    申请日：1981-08-18

    申请人： Lawrence G. Heller ,  Harry J. Jones ,  Harish N. Kotecha ,  Donald A. Soderman

    发明人： Lawrence G. Heller ,  Harry J. Jones ,  Harish N. Kotecha ,  Donald A. Soderman

    IPC分类号： H01L21/8234 ,  H01L27/07 ,  H01L27/105 ,  H01L29/08 ,  H01L29/10 ,  H01L21/26

    CPC分类号： H01L27/1055 ,  H01L21/823406 ,  H01L27/0733 ,  H01L29/0847 ,  H01L29/1045

    摘要： The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

    摘要翻译： 本发明是用于制造桶式装置的结构和工艺，其包括MOS电容器与MOSFET器件的合并以形成电荷转移电池。 在与漏极扩散相邻的FET器件的P型沟道区域的一部分中以第一浓度注入第一薄N型区域。 第二区域以与第一注入区域相邻并与第一注入区域连续的第一浓度的第二浓度注入N型掺杂剂。 第二区域中的N型浓度刚好足以补偿沟道区域中的P型背景掺杂。 这种结构增加了电池的电荷转移效率，并降低了其阈值电压对源极 -​​ 漏极电压的灵敏度。 用于器件的栅极在漏极上具有实质重叠，并且源极上的最小重叠，并且通过在栅极区域上保持均匀薄的氧化物层来最大化每单位面积的栅极至漏极电容。

    Method for fabricating self-aligned CCD devices and their output self-aligned MOS transistors on a single semiconductor substrate
    9.
    发明授权
    Method for fabricating self-aligned CCD devices and their output self-aligned MOS transistors on a single semiconductor substrate 失效
    在单个半导体衬底上制造自对准CCD器件及其输出自对准MOS晶体管的方法

    公开(公告)号：US4099317A

    公开(公告)日：1978-07-11

    申请号：US683361

    申请日：1976-05-05

    申请人： Stephen C. Su

    发明人： Stephen C. Su

    IPC分类号： H01L21/033 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/768 ,  B01J17/00

    CPC分类号： H01L29/66954 ,  H01L21/033 ,  H01L21/823406 ,  H01L29/76875

    摘要： The specification describes a self-aligning masking technique for the fabrication of charge coupled device-metal oxide semiconductor (CCD/MOS) transistor combinations. Both the CCD devices and the output MOS transistors are formed on the same semiconductor substrate during the same processing steps. Two layers of polycrystalline silicon, isolated from each other by a layer of dielectric material and isolated from the semiconductor substrate by another dielectric layer are used to form two sets of partially overlapping semiconductor strips. These strips and predetermined portions of the substrate are then doped, with a conductivity determining impurity opposite the conductivity type of the substrate. This process produces two self-aligned sets of gate electrodes for a two-phase or a four-phase CCD device and also produces two output self-aligned gate field effect transistors at the end of the CCD array.

    摘要翻译： 本说明书描述了用于制造电荷耦合器件 - 金属氧化物半导体（CCD / MOS）晶体管组合的自对准掩蔽技术。 在相同的处理步骤期间，CCD器件和输出MOS晶体管都形成在相同的半导体衬底上。 使用通过介电材料层彼此隔离并通过另一个介电层与半导体衬底隔离的两层多晶硅来形成两组部分重叠的半导体条。 然后将这些条和衬底的预定部分掺杂，其中电导率确定杂质与衬底的导电类型相反。 该过程为两相或四相CCD器件产生两个自对准的栅电极组，并且还在CCD阵列的末端产生两个输出自对准栅场效应晶体管。

    Silicon gate CCD structure
    10.
    发明授权
    Silicon gate CCD structure 失效
    硅栅CCD结构

    公开(公告)号：US4027382A

    公开(公告)日：1977-06-07

    申请号：US691657

    申请日：1976-06-01

    申请人： Al F. Tasch, Jr. ,  Robert C. Frye

    发明人： Al F. Tasch, Jr. ,  Robert C. Frye

    IPC分类号： H01L21/285 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/768 ,  B01J17/00

    CPC分类号： H01L29/66954 ,  H01L21/28525 ,  H01L21/823406 ,  H01L29/1062 ,  H01L29/76875

    摘要： Process for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

    摘要翻译： 制造具有边缘相邻电极并利用单一绝缘材料的两相电荷耦合器件（CCD）的工艺。 偏移自对准技术用于实现离子注入势阱或势垒区域的精确定位，以实现具有小位或电荷存储元件尺寸的CCD的每个栅极区域中的势阱（或阈值电压）所需的不对称性，导致 具有高填充密度的结构。 描述了表面和掩埋通道结构的制造。