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71.发明申请Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag 有权限制根据硬件模式和安全标志读取的指令的存储区公开(公告)号：US20110202739A1
公开(公告)日：2011-08-18
申请号：US12656786
申请日：2010-02-16
CPC分类号： G06F12/1491 , G06F21/52 , G06F21/74 , G06F21/79 , G06F2221/2105
摘要： An apparatus for processing data 2 includes a processor 8, a memory 6 and memory control circuitry 12. The processor 8 operates in a plurality of hardware modes including a privileged mode and a user mode. When operating in the privileged mode, the processor 8 is blocked by the memory control circuitry 12 from fetching instructions from memory address regions 34, 38, 42 within the memory 6 which are writeable within the user mode if a security flag within register 46 is set to indicate that this blocking mechanism is active.
摘要翻译： 处理数据2的装置包括处理器8，存储器6和存储器控制电路12.处理器8以包括特权模式和用户模式的多种硬件模式操作。 当在特权模式下操作时，处理器8被存储器控制电路12阻止从存储器6中的存储器地址区域34,38,42中获取指令，这些指令可在用户模式内写入，如果寄存器46内的安全标志被设置 以指示该阻塞机制是活动的。
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公开(公告)号：US07966466B2
公开(公告)日：2011-06-21
申请号：US12068449
申请日：2008-02-06
IPC分类号： G06F12/00
CPC分类号： G06F12/1483 , G06F9/30076
摘要： Access to memory address space is controlled by memory access control circuitry using access control data. The ability to change the access control data is controlled by domain control circuitry. Whether or not an instruction stored within a particular domain, being a set of memory addresses, is able to modify the access control data is dependent upon the domain concerned. Thus, the ability to change access control data can be restricted to instructions stored within particular defined locations within the memory address space thereby enhancing security. This capability allows systems to be provided in which call forwarding to an operating system can be enforced via call forwarding code and where trusted regions of the memory address space can be established into which a secure operating system may write data with increased confidence that that data will only be accessible by trusted software executing under control of a non-secure operating system.
摘要翻译： 使用访问控制数据的存储器访问控制电路控制对存储器地址空间的访问。 更改访问控制数据的能力由域控制电路控制。 作为一组存储器地址的存储在特定域内的指令是否能够修改访问控制数据取决于所涉及的域。 因此，改变访问控制数据的能力可以被限制为存储在存储器地址空间内的特定定义位置内的指令，从而增强安全性。 该功能允许提供系统，其中可以通过呼叫转移代码来实施对操作系统的呼叫转移，并且可以建立存储器地址空间的可信区域，安全操作系统可以以更高的置信度写入数据，该数据将 只能通过在非安全操作系统的控制下执行的可信软件来访问。
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公开(公告)号：US07506091B2
公开(公告)日：2009-03-17
申请号：US11603091
申请日：2006-11-22
摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.
摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储用于确定接收的中断信号I0-I9之间的优先级的优先权值P0-P9。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。
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74.发明授权Data transfer between an external data source and a memory associated with a data processor 有权外部数据源与与数据处理器相关联的存储器之间的数据传输公开(公告)号：US07254667B2
公开(公告)日：2007-08-07
申请号：US10815982
申请日：2004-04-02
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 operable to perform further data processing operations in response to receipt of said processor clock signal CLK. The two portions of the core being operable to be independently enabled such that one portion may be active while the other is inactive.
摘要翻译： 数据处理器核心10，其包括存储器访问接口部分30，其可操作以在外部数据源与至少一个与所述数据处理器核心相关联的存储器之间执行数据传输操作;以及数据处理部分12，可操作以执行另外的数据处理操作 接收所述处理器时钟信号CLK。 核心的两个部分可操作以独立地启用，使得一个部分可以是活动的，而另一个部分是不活动的。
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公开(公告)号：US07047401B2
公开(公告)日：2006-05-16
申请号：US10461335
申请日：2003-06-16
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3861
摘要： A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to respective memory locations or to store data values from multiple memory locations to respective program registers. A memory management unit 8 within the system stores device or strongly ordered memory attribute values which control whether or not a multiple memory access instruction involving such a memory location may be early terminated when an interrupt is received during its operation. Early termination is permitted in those circumstances where the multiple memory access instruction may be safely restarted and rerun in its entirety, whereas early termination is not permitted and the operation completes before the interrupt is taken in those circumstances where the memory locations are subject to a guaranteed number of memory accesses as this appears within the controlling program instructions.
摘要翻译： 数据处理装置2支持用于将来自多个程序寄存器16的数据值加载到相应存储器位置的多个存储器访问程序指令LDM，STM或将多个存储器位置的数据值存储到各个程序寄存器。 系统内的存储器管理单元8存储设备或强有序的存储器属性值，其控制在其操作期间接收到中断时是否可能提前终止涉及这样的存储器位置的多存储器访问指令。 在多重内存访问指令可以安全地重新启动并全部重新运行的情况下，允许提前终止，而不允许提前终止，并且在内存位置受到保证的情况下中断之前，操作完成 存储器访问次数显示在控制程序指令内。
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公开(公告)号：US07024543B2
公开(公告)日：2006-04-04
申请号：US10242671
申请日：2002-09-13
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： The present invention provides an apparatus and method for synchronizing a first pipeline and a second pipeline of a processor arranged to execute a sequence of instructions. The processor is arranged to route an instruction in the sequence through either the first or the second pipeline dependent on predetermined criteria, each pipeline having a plurality of pipeline stages including a retirement stage. Counter logic is provided for maintaining a first counter relating to the first pipeline and a second counter relating to the second pipeline. For each instruction in the first pipeline a determination is made as to when that instruction reaches a point within the first pipeline where an exception status of that instruction is resolved, and the counter logic is arranged to increment the first counter responsive to such determination. The processor is arranged to generate an indication within the second pipeline each time an instruction is routed to the first pipeline, and the counter logic is further arranged to increment the second counter responsive to that indication. Synchronisation logic is then provided which is arranged, when an instruction is in the retirement stage of the second pipeline, to determine with reference to the values of the first and second counters whether that instruction can be retired. If so, the retirement stage is arranged to cause an update of a state of the data processing apparatus dependent on the result of execution of that instruction.
摘要翻译： 本发明提供了一种用于使被配置为执行指令序列的处理器的第一流水线和第二流水线同步的装置和方法。 处理器被布置为依赖于预定标准来通过第一或第二流水线顺序地路由指令，每个流水线具有包括退休阶段的多个流水线阶段。 计数器逻辑被提供用于维持与第一流水线相关的第一计数器和与第二流水线相关的第二计数器。 对于第一流水线中的每个指令，确定何时该指令到达该指令的异常状态的第一流水线内的一个点，并且该计数器逻辑被布置成响应于这种确定来增加第一计数器。 处理器被布置为在每次将指令路由到第一流水线时在第二流水线内产生指示，并且计数器逻辑还被布置为响应于该指示递增第二计数器。 然后提供同步逻辑，当指令处于第二流水线的退休阶段时，其被配置为参考第一和第二计数器的值来确定该指令是否可以退休。 如果是这样，退休阶段被安排为依赖于该指令的执行结果来更新数据处理装置的状态。
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公开(公告)号：US09760374B2
公开(公告)日：2017-09-12
申请号：US13067805
申请日：2011-06-28
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30134 , G06F9/3824
摘要： A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.
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公开(公告)号：US08959318B2
公开(公告)日：2015-02-17
申请号：US13067808
申请日：2011-06-28
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F9/3861
摘要： A data processing system 2 supporting multiple modes of operation is provided with illegal change detecting circuitry 22 which detects attempts by program instructions to perform an illegal change of mode, such as a change to a higher level of privilege in response to execution of a mode changing program instruction or an exception return instruction. If such a change is detected, then an illegal change bit CPSR.IL is set. An instruction decoder 12 is responsive to the illegal change bit having a set value to treat subsequent program instructions as undefined instructions. These undefined instructions may then trigger an undefined instruction exception or other type of response.
摘要翻译： 提供了支持多种操作模式的数据处理系统2，其具有非法变化检测电路22，其检测由程序指令执行模式的非法改变的尝试，例如响应于模式改变的执行而改变为更高级别的特权 程序指令或异常返回指令。 如果检测到这种变化，则设置非法更改位CPSR.IL。 指令解码器12响应于具有设定值的非法变更位以将后续的程序指令视为未定义的指令。 这些未定义的指令可能会触发未定义的指令异常或其他类型的响应。
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公开(公告)号：US08713371B2
公开(公告)日：2014-04-29
申请号：US13296445
申请日：2011-11-15
IPC分类号： G06F11/00
CPC分类号： G06F11/3656 , G06F9/4812
摘要： A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus includes a data store for storing a current debug exception mask value. The data processing circuitry is configured to set the mask value to a first value in the data store in response to executing critical code and on termination of execution of the critical code to reset the mask value to not store the first value. The data processing circuitry is configured, in response to receipt of a control signal indicating a debug exception is to be taken, to allow the exception to be taken if the mask value is not set to the first value and not to allow said exception to be taken if the mask value is set to the first value.
摘要翻译： 一种用于响应于程序指令的执行和用于执行操作的调试电路执行数据处理操作的数据处理装置。 数据处理装置包括用于存储当前调试异常掩码值的数据存储器。 数据处理电路被配置为响应于执行关键代码并且终止关键代码的执行而将掩码值设置在数据存储器中的第一值以重置掩码值以不存储第一值。 数据处理电路被配置为响应于接收到指示调试异常的控制信号，以允许在掩码值未被设置为第一值而不允许所述异常为 如果掩码值被设置为第一个值则采取。
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公开(公告)号：US20140052921A1
公开(公告)日：2014-02-20
申请号：US14113723
申请日：2012-05-21
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/3834 , G06F12/0815 , G06F12/0817
摘要： A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
摘要翻译： 数据处理系统包括多个具有相关本地高速缓存存储器（12,14,16,18）并且耦合到相干互连电路（20）的交易主机（4,6,8,10）。 相干互连电路（20）内的监控电路（24）维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。
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