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260 条记录 (耗时 0.046 秒)

    Digital reliability monitor having autonomic repair and notification capability
    71.
    发明授权
    Digital reliability monitor having autonomic repair and notification capability 有权
    数字可靠性监控器具有自主修复和通知功能

    公开(公告)号：US07966537B2

    公开(公告)日：2011-06-21

    申请号：US12479914

    申请日：2009-06-08

    申请人： Anthony R. Bonaccio ,  Michael LeStrange ,  William R. Tonti ,  Sebastian T. Ventrone

    发明人： Anthony R. Bonaccio ,  Michael LeStrange ,  William R. Tonti ,  Sebastian T. Ventrone

    IPC分类号： G01R31/28

    CPC分类号： G06F1/04

    摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.

    摘要翻译： 一种用于防止集成电路故障的电路。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

    Band gap modulated optical sensor
    73.
    发明授权
    Band gap modulated optical sensor 有权
    带隙调制光传感器

    公开(公告)号：US07888266B2

    公开(公告)日：2011-02-15

    申请号：US12146560

    申请日：2008-06-26

    申请人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert Robison ,  William R. Tonti

    发明人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert Robison ,  William R. Tonti

    IPC分类号： H01L21/311

    CPC分类号： H01L27/1461 ,  H01L27/14645 ,  H01L27/14689

    摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.

    摘要翻译： 互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素 半导体层的材料。 电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。 因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。

    Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit
    76.
    发明授权
    Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit 失效
    使用绝缘体上半导体衬底制造的有源器件的器件结构和用于射频集成电路的设计结构

    公开(公告)号：US07709926B2

    公开(公告)日：2010-05-04

    申请号：US12108924

    申请日：2008-04-24

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7436 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

    摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

    摘要翻译： 用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。 器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域 比第一深度，以及半导体层中的第一掺杂区域。 第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。 装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。

    Back-End-of-Line Resistive Semiconductor Structures
    77.
    发明申请
    Back-End-of-Line Resistive Semiconductor Structures 有权
    后端电阻半导体结构

    公开(公告)号：US20100038754A1

    公开(公告)日：2010-02-18

    申请号：US12191683

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

    Patterned silicon-on-insulator layers and methods for forming the same
    78.
    发明授权
    Patterned silicon-on-insulator layers and methods for forming the same 有权
    图案化的绝缘体上硅层及其形成方法

    公开(公告)号：US07659599B2

    公开(公告)日：2010-02-09

    申请号：US12049258

    申请日：2008-03-14

    申请人： Roger Allen Booth, Jr. ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger Allen Booth, Jr. ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76243

    摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

    摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
    80.
    发明授权
    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
    具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法

    公开(公告)号：US07645645B2

    公开(公告)日：2010-01-12

    申请号：US11372334

    申请日：2006-03-09

    申请人： William P. Hovis ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    发明人： William P. Hovis ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

    摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。