公开(公告)号：US20160065693A1

公开(公告)日：2016-03-03

申请号：US14162557

申请日：2014-01-23

Applicant: D-WAVE SYSTEMS INC.

Inventor： Geordie Rose ,  Paul I. Bunyk

IPC: H04L29/08 ,  H04B10/70 ,  H04Q11/00 ,  G06N99/00 ,  H04L12/725

CPC classification number: H04L67/34 ,  G06F15/7825 ,  G06N99/002 ,  H04B10/70 ,  H04L45/306 ,  H04L67/327 ,  H04Q11/0066 ,  H04Q2011/0073

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

公开(公告)号：US20150332164A1

公开(公告)日：2015-11-19

申请号：US14727521

申请日：2015-06-01

Applicant: D-Wave Systems Inc.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H.S. Amin ,  Geordie Rose ,  David Grant ,  Miles F.H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06N99/00 ,  H04L29/08 ,  H03K3/38

CPC classification number: G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N99/002 ,  H03K3/38 ,  H04L67/12

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US20140229705A1

公开(公告)日：2014-08-14

申请号：US14175731

申请日：2014-02-07

Applicant: D-Wave Systems Inc.

Inventor： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H. S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC: G06F15/76

CPC classification number: G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N99/002 ,  H03K3/38 ,  H04L67/12

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract translation: 提供了用于解决各种计算问题的模拟处理器。 这种模拟处理器包括与多个耦合装置一起布置成格子的多个量子器件。 模拟处理器进一步包括偏置控制系统，每个偏置控制系统被配置为在对应的量子器件上施加局部有效偏置。 多个耦合装置中的一组耦合装置被配置为耦合格子中的最近邻量子器件。 另一组耦合器件配置成耦合下一个最近邻量子器件。 模拟处理器还包括多个耦合控制系统，每个耦合控制系统被配置为将多个耦合装置中的对应耦合装置的耦合值调谐到耦合。 这种量子处理器还包括一组读出装置，每个读出装置被配置为从多个量子器件中的对应的量子器件测量信息。

公开(公告)号：US20140228222A1

公开(公告)日：2014-08-14

申请号：US14255561

申请日：2014-04-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Mark W. Johnson ,  Paul I. Bunyk

IPC: G06N99/00 ,  H01L23/532

CPC classification number: G06N99/002 ,  B82Y10/00 ,  H01L23/53285 ,  H01L27/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract translation: 超导集成电路可以包括具有内部感应耦合元件和外部感应耦合元件的磁通量变换器，该外部感应耦合元件沿其长度的至少一部分围绕内部感应耦合元件。 磁通变压器可以具有类似同轴的几何形状，使得第一感应耦合元件和第二感应耦合元件之间的互感与将第一内部感应耦合元件与第一外部电感耦合器分开的距离成亚线性比例 元件。 第一电感耦合元件和第二电感耦合元件中的至少一个可以耦合到超导可编程器件，例如超导量子位。