公开(公告)号：US20090289280A1

公开(公告)日：2009-11-26

申请号：US12125853

申请日：2008-05-22

申请人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

发明人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor process and apparatus includes forming channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

摘要翻译： 半导体工艺和装置包括通过外延生长双轴向应力的硅锗沟道区域层（22）来形成具有增强的晶体管沟道区中的空穴迁移率的<100>沟道取向PMOS晶体管（34），单独或与 在形成覆盖在沟道区域层上的PMOS栅极结构（36）之前，然后在PMOS栅极结构上沉积中性（53）或压缩（55）接触蚀刻停止层之后的底层碳化硅层（86）。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

公开(公告)号：US20090242944A1

公开(公告)日：2009-10-01

申请号：US12059286

申请日：2008-03-31

申请人： Da Zhang ,  Christopher C. Hobbs ,  Srikanth B. Samavedam

发明人： Da Zhang ,  Christopher C. Hobbs ,  Srikanth B. Samavedam

IPC分类号： H01L29/00 ,  H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/823412 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

摘要翻译： 应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。 然后去除SMT膜。 在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。 这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。

公开(公告)号：US07572706B2

公开(公告)日：2009-08-11

申请号：US11680181

申请日：2007-02-28

申请人： Da Zhang ,  Brian A. Winstead

发明人： Da Zhang ,  Brian A. Winstead

IPC分类号： H01L21/336 ,  H01L21/8236

CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/7848

摘要： A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括形成覆盖衬底的栅极结构。 该方法还包括形成邻近栅极结构的侧壁间隔物。 该方法还包括在半导体器件的源极侧的方向上执行成角度的注入。 该方法还包括退火半导体器件。 该方法还包括在衬底中的侧壁间隔物的相对端附近形成凹部以暴露第一类型的半导体材料。 该方法还包括在凹槽中外延生长第二类型的半导体材料，其中第二类型的半导体材料具有不同于第一类型的半导体材料的晶格常数的晶格常数，以在半导体器件的沟道区域中产生应力 。

公开(公告)号：US07479422B2

公开(公告)日：2009-01-20

申请号：US11373536

申请日：2006-03-10

申请人： Brian A. Winstead ,  Ted R. White ,  Da Zhang

发明人： Brian A. Winstead ,  Ted R. White ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

摘要翻译： 一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。 该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。 该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。 该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是 使用第二种材料创建。

公开(公告)号：US07446026B2

公开(公告)日：2008-11-04

申请号：US11349595

申请日：2006-02-08

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823814 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.

摘要翻译： 一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底，在第一掺杂区域和第二掺杂区域上提供电介质，以及在电介质上至少形成第一栅极叠层 第一掺杂区域的一部分。 第一栅极堆叠包括电介质上的金属部分，金属部分上方的第一原位掺杂半导体部分以及原位掺杂半导体部分上的第一阻挡盖。 该方法还包括执行注入以形成与第一和第二栅极堆叠相邻的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡注入掺杂剂进入第一原位掺杂半导体部分的厚度。 源/漏嵌入式应力源也形成。

公开(公告)号：US20080203449A1

公开(公告)日：2008-08-28

申请号：US11680181

申请日：2007-02-28

申请人： Da Zhang ,  Brian A. Winstead

发明人： Da Zhang ,  Brian A. Winstead

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/7848

摘要： A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括形成覆盖衬底的栅极结构。 该方法还包括形成邻近栅极结构的侧壁间隔物。 该方法还包括在半导体器件的源极侧的方向上执行成角度的注入。 该方法还包括退火半导体器件。 该方法还包括在衬底中的侧壁间隔物的相对端附近形成凹部以暴露第一类型的半导体材料。 该方法还包括在凹槽中外延生长第二类型的半导体材料，其中第二类型的半导体材料具有不同于第一类型的半导体材料的晶格常数的晶格常数，以在半导体器件的沟道区域中产生应力 。

公开(公告)号：US07413970B2

公开(公告)日：2008-08-19

申请号：US11375894

申请日：2006-03-15

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L29/06 ,  H01L21/3205

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/66795 ,  H01L29/78684

摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

摘要翻译： 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

公开(公告)号：US20080014688A1

公开(公告)日：2008-01-17

申请号：US11428953

申请日：2006-07-06

申请人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Da Zhang

发明人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Da Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

摘要翻译： 半导体制造工艺包括掩蔽半导体晶片的第一区域（例如，NMOS区域），例如双轴拉伸应变绝缘体上硅（SOI）晶片，并在第二晶片区域的源/漏区域中产生凹陷，例如 ，PMOS区域。 然后将晶片在促进硅迁移的环境中退火。 源极/漏极凹槽用源极/漏极结构填充，例如通过外延生长。 退火环境可以包括保持在约800至1000℃范围内的温度的含氢物质，例如H 2 H 2或GeH 2 H 2。第二区域 可以是硅，并且源极/漏极结构可以是硅锗。 创建凹槽可以包括用第一蚀刻工艺创建浅凹槽，执行非晶化注入以产生非晶层，执行惰性环境退火以使非晶层重结晶，以及用第二蚀刻工艺加深浅凹槽。

公开(公告)号：US07282415B2

公开(公告)日：2007-10-16

申请号：US11092291

申请日：2005-03-29

申请人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

发明人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

摘要翻译： 通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。 在控制电极的侧壁附近形成绝缘层。 注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下 半导体器件。 第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。 在第一和第二沟槽内形成有相对于半导体衬底具有不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。

公开(公告)号：US20070238250A1

公开(公告)日：2007-10-11

申请号：US11393340

申请日：2006-03-30

申请人： Da Zhang ,  Ted White ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Ted White ,  Bich-Yen Nguyen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78684

摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

摘要翻译： 半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 使用加热到约75℃温度的NH 4 OH：H 2 O 2的溶液进行湿蚀刻可以用于蚀刻源/漏区。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。