公开(公告)号：US09111908B2

公开(公告)日：2015-08-18

申请号：US13448531

申请日：2012-04-17

Applicant: Ted R. White ,  Gowrishankar L. Chindalore ,  Brian A. Winstead

Inventor： Ted R. White ,  Gowrishankar L. Chindalore ,  Brian A. Winstead

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/7881

Abstract: Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Abstract translation: 实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。 在选择栅极和控制栅极之间形成电荷存储层。 选择栅极使用第一导电层和第二导电层形成。 第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。 在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。 在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。

公开(公告)号：US08390026B2

公开(公告)日：2013-03-05

申请号：US11559642

申请日：2006-11-14

Applicant: Brian A. Winstead ,  Ted R. White

Inventor： Brian A. Winstead ,  Ted R. White

IPC: H01L29/78 ,  H01L21/04

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78687

Abstract: An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.

Abstract translation: 电子器件可以包括具有第一沟道区的第一晶体管，该第一沟道区还包括在一个方面为至多约5nm厚的异质结区。 在另一方面，第一晶体管可以包括p沟道晶体管，其包括具有与相关沟道区不匹配的功函数的栅极，并且异质结区可以沿着比相对表面更靠近衬底的半导体层的表面 的基底。 电子设备还可以包括n沟道晶体管，并且p沟道和n沟道晶体管的亚阈值载流子深度可以具有与彼此相差大致相同的值。 形成电子器件的方法可以包括形成具有大于约1.2eV的能带隙的化合物半导体层。

公开(公告)号：US07927956B2

公开(公告)日：2011-04-19

申请号：US11609664

申请日：2006-12-12

Applicant: Marius K. Orlowski ,  Alexander L. Barr ,  Mariam G. Sadaka ,  Ted R. White

Inventor： Marius K. Orlowski ,  Alexander L. Barr ,  Mariam G. Sadaka ,  Ted R. White

IPC: H01L21/331 ,  H01L21/8222

CPC classification number: H01L29/1054 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  Y10S438/933

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract translation: 提供了具有硅层的半导体衬底。 在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。 在硅层上形成非晶或多晶硅锗层。 或者，将锗注入硅层的顶部以形成非晶硅锗层。 然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。 然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。 在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。 或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

公开(公告)号：US20110031548A1

公开(公告)日：2011-02-10

申请号：US12909027

申请日：2010-10-21

Applicant: TED R. WHITE ,  BRIAN A. WINSTEAD

Inventor： TED R. WHITE ,  BRIAN A. WINSTEAD

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/11521 ,  H01L29/42328

Abstract: A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

Abstract translation: 提供一种非易失性存储单元，其包括其中形成有源极区和限定在源极区和漏极区之间的沟道区的漏极区的衬底。 非易失性存储单元还包括覆盖通道区域的第一部分的选择栅极结构。 非易失性存储单元还包括形成在通道区域的第二部分上的控制栅极结构，其中控制栅极结构包括具有高度的纳米晶体堆叠，其中控制栅极结构在形成在 基本上平行于基板的顶表面的第一平面的交叉点和基本上平行于控制栅结构的侧表面的第二平面，其中，角区域中的控制栅结构的半径与 纳米晶体堆叠至少为0.5。

公开(公告)号：US07811382B2

公开(公告)日：2010-10-12

申请号：US11421009

申请日：2006-05-30

Applicant: Mariam G. Sadaka ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

Inventor： Mariam G. Sadaka ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

IPC: C30B21/02

CPC classification number: C30B29/52 ,  C30B25/02 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76254

Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.

Abstract translation: 具有应变的硅层的晶片用于形成晶体管。 通过首先在施主晶片上形成具有松弛应变的至少30％的锗的锗锗（SiGe）层来形成硅层。 外延生长薄硅层以在松弛的SiGe层上具有拉伸应变。 拉伸应变量与锗浓度有关。 优选在800至850摄氏度之间的温度下，通过使二氯硅烷和一氧化二氮反应，在薄硅层上形成高温氧化物（HTO）层。 手柄晶片设置有支撑基板和氧化物层，然后将其结合到HTO层。 高密度的HTO层能够保持薄硅层的拉伸应变。 松弛的SiGe层被切割，然后蚀刻掉以露出薄的硅层。 然后在优选不超过500摄氏度的温度下使用丙硅烷在薄硅层上外延生长与低硅薄层的拉伸应变相关的低温硅层。 因此，与薄硅层的应变相关的所得拉伸应变也与弛豫SiGe层的锗浓度相关。 在低温下使用丙硅烷的低温硅层的厚度明显大于该拉伸应变的硅层通常预期的厚度。

公开(公告)号：US07803670B2

公开(公告)日：2010-09-28

申请号：US11458902

申请日：2006-07-20

Applicant: Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

Inventor： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

IPC: H01L21/00

CPC classification number: H01L21/845 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract translation: 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。

公开(公告)号：US07737496B2

公开(公告)日：2010-06-15

申请号：US11836844

申请日：2007-08-10

Applicant: Voon-Yew Thean ,  Brian J. Goolsby ,  Linda B. McCormick ,  Bich-Yen Nguyen ,  Colita M. Parker ,  Mariam G. Sadaka ,  Victor H. Vartanian ,  Ted R. White ,  Melissa O. Zavala

Inventor： Voon-Yew Thean ,  Brian J. Goolsby ,  Linda B. McCormick ,  Bich-Yen Nguyen ,  Colita M. Parker ,  Mariam G. Sadaka ,  Victor H. Vartanian ,  Ted R. White ,  Melissa O. Zavala

IPC: H01L21/84

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

公开(公告)号：US07556992B2

公开(公告)日：2009-07-07

申请号：US11496106

申请日：2006-07-31

Applicant: Zhonghai Shi ,  Voon-Yew Thean ,  Ted R. White

Inventor： Zhonghai Shi ,  Voon-Yew Thean ,  Ted R. White

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/785

Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a crystallographic orientation and a second semiconductor layer (405) having a crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

Abstract translation: 提供一种用于制造半导体器件的方法，包括（a）提供包括具有<110>晶体取向的第一半导体层（407）和具有<100>晶体取向的第二半导体层（405）的半导体堆叠; （b）在第一半导体层中限定氧化物掩模（415）; 和（c）利用该氧化物掩模对第二半导体层进行图案化。

公开(公告)号：US20080274594A1

公开(公告)日：2008-11-06

申请号：US11742755

申请日：2007-05-01

Applicant: Gauri V. Karve ,  Debby Eades ,  Gregory S. Spencer ,  Ted R. White

Inventor： Gauri V. Karve ,  Debby Eades ,  Gregory S. Spencer ,  Ted R. White

IPC: H01L21/8238 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

Abstract: A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.

Abstract translation: 当抛光外延半导体层（99）进行DSO和BOS积分时，半导体工艺和装置通过去除氮化物掩模层（96）并使用氧化物抛光停止层（92）来提供平面化的混合衬底（16）。 为此，形成初始SOI晶片半导体堆叠（11），其包括在SOI半导体层（90）和氮化物掩模层（93）之间形成的一个或多个氧化物抛光停止层（91,92）。 氧化物抛光停止层（92）可以通过沉积厚度为约100-250埃的TEOS致密的LPCVD层来形成。

公开(公告)号：US07288458B2

公开(公告)日：2007-10-30

申请号：US11302770

申请日：2005-12-14

Applicant: Olubunmi O. Adetutu ,  Robert E. Jones ,  Ted R. White

Inventor： Olubunmi O. Adetutu ,  Robert E. Jones ,  Ted R. White

IPC: H01L21/331 ,  H01L21/8222

CPC classification number: H01L21/76254 ,  H01L21/02002

Abstract: A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.