公开(公告)号：US20090271751A1

公开(公告)日：2009-10-29

申请号：US12111634

申请日：2008-04-29

申请人： HANIF FATEMI ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： HANIF FATEMI ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G01R31/318371

摘要： In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip and selecting at least one path that maximizes the process coverage metric.

摘要翻译： 在一个实施例中，本发明是用于速度测试的统计路径选择的方法和装置。 用于选择用于高速测试的集成电路芯片的路径的方法的一个实施例包括计算集成电路芯片中的多个路径的处理覆盖度量度，并且选择使过程覆盖度量最大化的至少一个路径。

公开(公告)号：US20070234252A1

公开(公告)日：2007-10-04

申请号：US11358622

申请日：2006-02-21

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/509 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/10 ,  G06F2217/12 ,  Y02P90/265

摘要： The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit, the method comprising: conducting a statistical timing analysis; expressing a statistical circuit delay in terms of a delay of the edge; and computing a gradient of the statistical circuit delay with respect to parameters of the delay of the edge.

摘要翻译： 本发明提供了一种方法，系统和程序产品，用于相对于电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度。 本发明的第一方面提供了一种用于根据电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度的方法，所述方法包括：进行统计时序分析; 根据边缘的延迟表示统计电路延迟; 以及计算相对于边缘的延迟的参数的统计电路延迟的梯度。

公开(公告)号：US08359563B2

公开(公告)日：2013-01-22

申请号：US12542042

申请日：2009-08-17

申请人： Soroush Abbaspour ,  Peter Feldmann ,  David Ling ,  Chandramouli Visweswariah

发明人： Soroush Abbaspour ,  Peter Feldmann ,  David Ling ,  Chandramouli Visweswariah

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.

摘要翻译： 在一个实施例中，本发明是用于静态时序分析的基于时刻的表征波形。 用于将与集成电路的栅极相关联的定时波形映射到表征波形的方法的一个实施例包括使用处理器执行步骤，包括：计算定时波形的一个或多个时刻并根据时刻定义表征波形 。

公开(公告)号：US20110191055A1

公开(公告)日：2011-08-04

申请号：US12696902

申请日：2010-01-29

申请人： JOSE MARTINEZ ,  Chandramouli Visweswariah ,  Francis Woytowich ,  Jinjun Xiong

发明人： JOSE MARTINEZ ,  Chandramouli Visweswariah ,  Francis Woytowich ,  Jinjun Xiong

IPC分类号： G06F19/00 ,  G01R31/00 ,  G06F17/18

CPC分类号： G01R31/00 ,  G06F17/18 ,  G06F19/00

摘要： In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.

摘要翻译： 在一个实施例中，本发明是用于选择在速度测试中使用的电压和频率水平的方法和装置。 用于选择用于测试集成电路芯片的一组测试条件的方法的一个实施例包括制定统计优化问题并获得统计优化问题的解决方案，其中解是测试条件集合。

公开(公告)号：US20080072184A1

公开(公告)日：2008-03-20

申请号：US11942034

申请日：2007-11-19

申请人： Jun Zhou ,  David Hathaway ,  Chandramouli Visweswariah ,  Patrick Williams

发明人： Jun Zhou ,  David Hathaway ,  Chandramouli Visweswariah ,  Patrick Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US5886908A

公开(公告)日：1999-03-23

申请号：US825278

申请日：1997-03-27

申请人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

发明人： Andrew Roger Conn ,  Rudolf Adriaan Haring ,  Chandramouli Visweswariah

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： A method of efficient computation of gradients of a merit function of a system includes the steps of: specifying at least one parameter for which the gradients with respect to the at least one parameter are desired; specifying the merit function of interest in terms of observable measurements of the system; either solving or simulating the system to determine values of the measurements; expressing the gradients of the merit function as the gradient of a weighted sum of measurements; forming an appropriately configured adjoint system; and either solving or simulating the adjoint system to simultaneously determine the gradients of the merit function with respect to the at least one parameter by employing a single adjoint analysis. Preferably, the system may be modeled by a set of equations comprising at least one of the following: a nonlinear set of equations, a linear set of equations, a set of linear partial differential equations, a set of nonlinear partial differential equations, a set of linear differential algebraic equations or a set of nonlinear differential algebraic equations. Further, the system of interest may be a network and, preferably, may be an electrical circuit. Still further, elements of the adjoint network and excitations of the adjoint network are determined in order to obtain the gradients of the merit function by employing a single adjoint analysis. It is to be appreciated that, in a preferred embodiment, the gradients of merit function are computed for the purpose of optimization and the merit function may be either a Lagrangian merit function or an augmented Lagrangian merit function.

摘要翻译： 一种有效计算系统的优值函数的梯度的方法包括以下步骤：指定至少一个参数，该参数相对于至少一个参数的梯度是期望的; 根据系统的可观测量指定感兴趣的优点功能; 解决或模拟系统以确定测量值; 将优值函数的梯度表示为加权求和和的梯度; 形成适当配置的伴随系统; 并且通过采用单一伴随分析来解决或模拟伴随系统以同时确定关于至少一个参数的优值函数的梯度。 优选地，可以通过包括以下至少一个的一组方程来建模系统：非线性方程组，线性方程组，一组线性偏微分方程，一组非线性偏微分方程，一组 的线性微分代数方程或一组非线性微分代数方程。 此外，感兴趣的系统可以是网络，并且优选地可以是电路。 此外，确定伴随网络的元素和伴随网络的激励，以便通过采用单个伴随分析来获得优值函数的梯度。 应当理解，在优选实施例中，为优化目的而计算优值函数的梯度，并且优值函数可以是拉格朗日优值函数或增强的拉格朗日优值函数。

公开(公告)号：US07958484B2

公开(公告)日：2011-06-07

申请号：US11836842

申请日：2007-08-10

申请人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

IPC分类号： G06F17/50 ,  G06F13/00

CPC分类号： G06F17/5031 ,  G06K9/6226 ,  G06K9/6247

摘要： A method for partitioning the columns of a matrix A. The method includes providing the matrix A in a memory device of a computer system. The matrix A has n columns and m rows, wherein n is an integer of at least 3, and wherein m is an integer of at least 1. The method further includes executing an algorithm by a processor of the computer system. Executing the algorithm includes partitioning the n columns of the matrix A into a closed group of p clusters, wherein p is a positive integer of at least 2 and less than n, wherein the partitioning includes an affinity-based merging of clusters of the matrix A, and wherein each cluster is a collection of one or more columns of A.

摘要翻译： 用于分割矩阵A的列的方法。该方法包括将矩阵A提供到计算机系统的存储器设备中。 矩阵A具有n列和m行，其中n是至少为3的整数，并且其中m是至少为1的整数。该方法还包括由计算机系统的处理器执行算法。 执行算法包括将矩阵A的n列划分成闭合的p个群集，其中p是至少为2且小于n的正整数，其中分区包括基于关系的矩阵A的簇的合并 ，并且其中每个聚类是A的一列或多列的集合。

公开(公告)号：US07698674B2

公开(公告)日：2010-04-13

申请号：US11565803

申请日：2006-12-01

申请人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Revanta Banerji ,  David J. Hathaway ,  Jessica Sheridan ,  Chandramouli Visweswariah

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

摘要翻译： 一种用于在电路的两个点之间具有多个点到点延迟约束的电路上执行静态时序分析的方法和系统，其中针对所有类型的点导出两个保守和两个乐观用户定义的测试 到点延迟约束。 该方法表明，当进行保守测试而不引入任何特殊标签时，发现点对点约束得到满足。 另一方面，当乐观测试失败而没有任何特殊标签时，如果引入特殊标签，则确定点对点约束必然会失败，在这种情况下，仅当确切的松弛时才引入它们 是希望的。 最后，对于两者之间的任何东西，需要使用特殊标签或路径跟踪进行真正的分析。 基于图形的拓扑结构，在某些情况下，基于到达时间的测试可能更紧密，而所需到达时间的测试可能在其他情况下更严格。

公开(公告)号：US20090150844A1

公开(公告)日：2009-06-11

申请号：US11954138

申请日：2007-12-11

申请人： Vikram Iyengar ,  David E. Lackey ,  Subbayyan Venkatesan ,  Chandramouli Visweswariah ,  Jinjun Xiong

发明人： Vikram Iyengar ,  David E. Lackey ,  Subbayyan Venkatesan ,  Chandramouli Visweswariah ,  Jinjun Xiong

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output.

摘要翻译： 关键路径选择的方法提供了一组最初不包含路径的路径。 定时工具用于识别集成电路设计的潜在关键路径。 如果潜在的关键路径内的逻辑设备被小于路径集合内预定数量的关键路径共享，则评估每个潜在的关键路径并将潜在的关键路径添加到路径集合。 对于每个潜在的关键路径重复该评估和添加过程，直到所有潜在的关键路径都被评估为止。 然后，可以输出该组路径内的潜在关键路径。

公开(公告)号：US07428716B2

公开(公告)日：2008-09-23

申请号：US10666353

申请日：2003-09-19

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form.

摘要翻译： 本发明是考虑到统计延迟变化的数字电路的统计或概率静态时序分析的系统和方法。 假设每个门或线的延迟由标称部分，由每个变化源参数化的相关随机部分和独立的随机部分组成。 考虑到相关性，到达时间和所需到达时间作为参数化随机变量传播。 包括早期模式和晚期模式时序; 处理组合和顺序电路; 静态CMOS以及动态逻辑系列。 时间分析复杂度在图形的大小和变异的数量上是线性的。 结果是定时报告，其中所有定时量（如到达时间和休息）以参数化形式报告为概率分布。