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公开(公告)号：US20110276727A1
公开(公告)日：2011-11-10
申请号：US12857716
申请日：2010-08-17
CPC分类号： G06F13/1684 , G06F13/161
摘要： An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.
摘要翻译： 一种包括仲裁器电路，协议引擎电路和信道路由器电路的装置。 仲裁器电路可以被配置为基于第一准则从多个信道请求中确定获胜信道。 多个信道请求中的每一个可以表示具有与存储器的地址边界对准的固定长度的数据突发。 协议引擎电路可以被配置为从仲裁器电路接收指示获胜信道的信号。 协议引擎电路还可以被配置为以等于数据突发的粒度执行存储器协议。 信道路由器电路可以被配置为向仲裁器电路和协议引擎电路呈现多个信道请求。
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公开(公告)号：US20110185111A1
公开(公告)日：2011-07-28
申请号：US12691819
申请日：2010-01-22
申请人： Robert W. Warren , Robb Mankin , Buddy Scott Holt
发明人： Robert W. Warren , Robb Mankin , Buddy Scott Holt
IPC分类号： G06F12/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C2211/5641
摘要： Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit.
摘要翻译： 本发明的各种实施例提供了多位存储器单元的延长的使用寿命。 作为示例，本发明的一些实施例提供了包括多个多位存储器单元，编码电路和解码电路的电子系统。 多个多位存储器单元中的每一个可操作以保持至少两个位。 编码电路可操作以接收包括至少两个数据位的数据输入，并将两个数据位编码为多个多位存储器单元的编码输出。 编码输出可以选择为表示两位的单个2位输出，或表示两位的一系列两位两位输出。 解码电路可操作以反转编码电路所应用的编码。
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73.发明申请Systems and Methods for Implementing Error Correction in Relation to a Flash Memory 有权用于实现与闪存相关的纠错的系统和方法公开(公告)号：US20110060968A1
公开(公告)日：2011-03-10
申请号：US12774077
申请日：2010-05-05
申请人： Robert W. Warren
发明人： Robert W. Warren
CPC分类号： G06F11/1068 , G11C7/1006 , G11C16/10 , G11C2029/0411
摘要： Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.
摘要翻译： 本发明的各种实施例提供用于存储器及其利用的系统，方法和电路。 作为一个示例，公开了一种包括闪存器件和闪存存取电路的存储器系统。 闪存访问电路可操作以在数据集上执行错误代码编码算法以产生错误代码，以将数据集写入第一位置的闪速存储器件，并将错误代码写入闪存器件 第二个位置。
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74.发明申请公开(公告)号：US20100306580A1
公开(公告)日：2010-12-02
申请号：US12473437
申请日：2009-05-28
CPC分类号： G06F12/0246 , G06F2212/1036 , G11C16/349 , G11C29/76
摘要： Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.
摘要翻译： 本发明的各种实施例提供用于数据存储的系统和方法。 作为示例，公开了包括多个存储块，不可靠块识别电路和部分故障指示电路的存储设备。 多个存储块中的每一个包括多个存储单元，随着访问时存储单元的可靠性随着时间的推移而降低。 所述不可靠块识别电路可操作以确定所述多个存储器块中的一个或多个不可靠，并且所述部分故障指示电路可操作以在确定所述多个存储块中的数量不足的情况下不允许对所述多个存储器块的写入访问 内存块保持可靠。
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公开(公告)号：US07635606B2
公开(公告)日：2009-12-22
申请号：US11800379
申请日：2007-05-05
申请人： Robert W. Warren , Gene Gan , Tony LoBianco
发明人： Robert W. Warren , Gene Gan , Tony LoBianco
IPC分类号： H01L21/00
CPC分类号： B81C1/00333 , B81C2203/0136 , H01L21/56 , H01L23/3114 , H01L23/315 , H01L24/48 , H01L25/50 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/7511 , H01L2924/00014 , H01L2924/12044 , H01L2924/1461 , H01L2924/16235 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to one exemplary embodiment, a method for forming a wafer level package includes fabricating an active device on a substrate in a semiconductor wafer, forming polymer walls around the active device, and applying a blanket film over the semiconductor wafer and the polymer walls to house the active device in a substantially enclosed cavity formed by the polymer walls and the blanket film. By way of examples and without limitation, the active device can be a microelectromechanical systems (“MEMS”) device, a bulk acoustic wave (“BAW”) filter, or a surface acoustic wave (“SAW”) filter. According to one embodiment, solder bumps can be applied to interconnect traces of the active device, and the semiconductor wafer can then be diced to form an individual die. According to another embodiment, the semiconductor wafer can be diced to form an individual die, then the individual die is wire bonded to a circuit board.
摘要翻译： 根据一个示例性实施例，用于形成晶片级封装的方法包括在半导体晶片中的衬底上制造有源器件，在有源器件周围形成聚合物壁，以及在半导体晶片和聚合物壁上施加覆盖膜以容纳 该有源器件位于由聚合物壁和覆盖膜形成的基本上封闭的空腔中。 作为示例而非限制，有源器件可以是微机电系统（“MEMS”）器件，体声波（“BAW”）滤波器或表面声波（“SAW”）滤波器。 根据一个实施例，可以施加焊料凸块来互连有源器件的迹线，然后可以对半导体晶片进行切割以形成单个管芯。 根据另一实施例，可以对半导体晶片进行切割以形成单个管芯，然后将单个管芯接合到电路板上。
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公开(公告)号：US20090243086A1
公开(公告)日：2009-10-01
申请号：US12365101
申请日：2009-02-03
申请人： Robert W. Warren
发明人： Robert W. Warren
CPC分类号： H01L23/4334 , H01L24/48 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor chip, a thermal adhesive is used to bond an internal heat spreader to an active functional die. In an alternative embodiment a dummy die is place directly on top of the active functional die and a thermal adhesive is used to bond an internal heat spreader to the dummy die. This provides a direct and relatively low thermal conductivity path from the heat source, i.e., the functional device to the top of the package, that is, the internal metal heat spreader which is also exposed to the air.
摘要翻译： 在半导体芯片中，使用热粘合剂将内部散热器连接到活性功能模具。 在替代实施例中，将虚拟模具直接放置在活性功能模具的顶部上，并且使用热粘合剂将内部散热器粘合到模具上。 这提供了从热源即功能装置到包装顶部的直接且相对较低的导热路径，即也暴露于空气的内部金属散热器。
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77.发明授权Using data compression to achieve lower linear bit densities on a storage medium 有权使用数据压缩来实现存储介质上较低的线性位密度公开(公告)号：US07133228B2
公开(公告)日：2006-11-07
申请号：US10683973
申请日：2003-10-10
IPC分类号： G11B5/09
CPC分类号： G11B20/1217 , G11B20/00007 , G11B20/10 , G11B2020/1222 , G11B2020/1287 , G11B2020/1298 , G11B2220/2516
摘要： Method and apparatus for transferring data to and from a data storage medium, such as a rotatable disc in a data storage device. The medium includes a data sector field with a physical length sufficient to store a first data block at a first write frequency. A compression engine compresses the first data block to provide a reduced size, compressed data block. The compressed data block is then written to the data sector field at a second write frequency less than the first write frequency so that the written compressed data block occupies substantially the physical length of said data sector field. This achieves a decreased linear bit density and tends to increase communication channel signal to noise (SNR) ratios and reduce error rates. Data slipping is further advantageously employed so that the first data block further stores at least a portion of a second compressed data block.
摘要翻译： 用于向数据存储介质（例如数据存储设备中的可旋转盘）传送数据和从数据存储介质传送数据的方法和装置。 介质包括具有足以存储第一写入频率的第一数据块的物理长度的数据扇区字段。 压缩引擎压缩第一数据块以提供减小尺寸的压缩数据块。 然后，压缩数据块以小于第一写入频率的第二写入频率被写入数据扇区字段，使得所写入的压缩数据块基本上占据所述数据扇区字段的物理长度。 这实现了线性位密度的降低，并且倾向于增加通信信道信噪比（SNR）比并降低误码率。 更有利地采用数据滑移，使得第一数据块还存储第二压缩数据块的至少一部分。
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公开(公告)号：US06862151B2
公开(公告)日：2005-03-01
申请号：US09896782
申请日：2001-06-28
CPC分类号： G06F3/0619 , G06F3/0656 , G06F3/0674 , G11B19/04 , G11B20/10527 , G11B20/18
摘要： A procedure for reading data stored on a data storage disc in a disc drive is disclosed. The procedure involves reading data from one or more sectors on the data storage disc after an error occurred while initially reading the sector(s) pursuant to a read command issued by a host computer. During the initial read, the procedure logs information pertaining to the sector(s) on the disc where an error occurred. The logged information is then used during the procedure to retrieve data from the sector(s) in a single revolution of the disc. The procedure uses a skip mask, a vector buffer management list and a data throttling mechanism to administer a transfer of data from a disc to a host computer via a data buffer.
摘要翻译： 公开了一种用于读取存储在盘驱动器中的数据存储盘上的数据的过程。 该过程涉及在根据由主计算机发出的读取命令最初读取扇区时发生错误之后从数据存储盘上的一个或多个扇区读取数据。 在初始读取期间，该过程记录与发生错误的盘上的扇区有关的信息。 然后在该过程中使用所记录的信息，以在光盘的一次旋转中从扇区中检索数据。 该过程使用跳过掩码，向量缓冲器管理列表和数据限制机制来管理通过数据缓冲器将数据从盘传输到主计算机。
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