公开(公告)号：US20130042064A1

公开(公告)日：2013-02-14

申请号：US13566204

申请日：2012-08-03

申请人： Horia Simionescu ,  Mark Ish ,  Luca Bert ,  Robert Quinn ,  Earl T. Cohen ,  Timothy Canepa

发明人： Horia Simionescu ,  Mark Ish ,  Luca Bert ,  Robert Quinn ,  Earl T. Cohen ,  Timothy Canepa

IPC分类号： G06F12/08

CPC分类号： G06F12/0871 ,  G06F2212/401

摘要： The present disclosure is directed to a system for dynamically adaptive caching. The system includes a storage device having a physical capacity for storing data received from a host. The system may also include a control module for receiving data from the host and compressing the data to a compressed data size. Alternatively, the data may also be compressed by the storage device. The control module may be configured for determining an amount of available space on the storage device and also determining a reclaimed space, the reclaimed space being according to a difference between the size of the data received from the host and the compressed data size. The system may also include an interface module for presenting a logical capacity to the host. The logical capacity has a variable size and may include at least a portion of the reclaimed space.

摘要翻译： 本公开涉及用于动态自适应缓存的系统。 该系统包括具有用于存储从主机接收的数据的物理容量的存储装置。 该系统还可以包括用于从主机接收数据并将数据压缩到压缩数据大小的控制模块。 或者，数据也可以被存储设备压缩。 控制模块可以被配置用于确定存储设备上的可用空间量，并且还确定回收空间，所述回收空间根据从主机接收的数据的大小与压缩数据大小之间的差异。 该系统还可以包括用于向主机呈现逻辑容量的接口模块。 逻辑容量具有可变大小并且可以包括至少部分回收空间。

公开(公告)号：US08244969B2

公开(公告)日：2012-08-14

申请号：US13149851

申请日：2011-05-31

申请人： Thomas M. McWilliams ,  Earl T. Cohen ,  James M. Bodwin ,  Ulrich Bruening

发明人： Thomas M. McWilliams ,  Earl T. Cohen ,  James M. Bodwin ,  Ulrich Bruening

IPC分类号： G06F12/00

CPC分类号： G06F12/0284 ,  G06F12/0802 ,  G06F12/0806 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/2542 ,  G06F2212/401 ,  Y02D10/13

摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

摘要翻译： 数据处理系统包括一个或多个节点，每个节点包括存储器子系统。 子系统包括细粒度的存储器和较细粒度的（例如基于页面的）存储器。 细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。 在系统上执行的软件使用节点地址空间，其能够访问所有节点的基于页面的存储器。 每个节点可选地为该空间的至少一部分提供ACID存储器属性。 在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。 在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

公开(公告)号：US20110289263A1

公开(公告)日：2011-11-24

申请号：US13149851

申请日：2011-05-31

申请人： Thomas M. McWilliams ,  Earl T. Cohen ,  James M. Bodwin ,  Ulrich Bruening

发明人： Thomas M. McWilliams ,  Earl T. Cohen ,  James M. Bodwin ,  Ulrich Bruening

IPC分类号： G06F12/02

CPC分类号： G06F12/0284 ,  G06F12/0802 ,  G06F12/0806 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/2542 ,  G06F2212/401 ,  Y02D10/13

摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

摘要翻译： 数据处理系统包括一个或多个节点，每个节点包括存储器子系统。 该子系统包括细粒度的存储器和不太细粒度的（例如基于页面的）存储器。 细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。 在系统上执行的软件使用节点地址空间，其能够访问所有节点的基于页面的存储器。 每个节点可选地为该空间的至少一部分提供ACID存储器属性。 在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。 在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

公开(公告)号：US07567508B2

公开(公告)日：2009-07-28

申请号：US11134898

申请日：2005-05-23

申请人： Anna Charny ,  Christopher Kappler ,  Sandeep Bajaj ,  Earl T. Cohen

发明人： Anna Charny ,  Christopher Kappler ,  Sandeep Bajaj ,  Earl T. Cohen

IPC分类号： H04L12/26 ,  H04L12/56 ,  G06F15/173 ,  G06F5/00

CPC分类号： H04L47/10 ,  H04L47/2408 ,  H04L47/2416 ,  H04L47/2441 ,  H04L47/283 ,  H04L47/32 ,  H04L49/90 ,  H04L49/9015 ,  H04L49/9084 ,  H04L49/9094

摘要： A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.

摘要翻译： 公开了一种用于提供延迟限制和优先级分组丢弃的方法和系统。 系统限制配置为以FIFO顺序传送数据包的队列的大小，基于指定的延迟限制的阈值。 如果不超过阈值，接收到的数据包将排队。 如果超出阈值，丢弃优先级小于接收报文优先级的报文。 如果队列中的所有数据包的优先级大于接收到的数据包，则超过阈值时，接收到的数据包将被丢弃。

公开(公告)号：US20080301256A1

公开(公告)日：2008-12-04

申请号：US12130661

申请日：2008-05-30

申请人： Thomas M. McWilliams ,  Earl T. Cohen ,  James M. Bodwin ,  Ulrich Bruening

发明人： Thomas M. McWilliams ,  Earl T. Cohen ,  James M. Bodwin ,  Ulrich Bruening

IPC分类号： G06F15/167 ,  G06F11/28

CPC分类号： G06F12/0284 ,  G06F12/0802 ,  G06F12/0806 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/2542 ,  G06F2212/401 ,  Y02D10/13

摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses n node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

摘要翻译： 数据处理系统包括一个或多个节点，每个节点包括存储器子系统。 该子系统包括细粒度的存储器和不太细粒度的（例如基于页面的）存储器。 细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。 系统上执行的软件使用n个节点地址空间，可以访问所有节点的基于页面的存储器。 每个节点可选地为该空间的至少一部分提供ACID存储器属性。 在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。 在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

公开(公告)号：US07453898B1

公开(公告)日：2008-11-18

申请号：US10339032

申请日：2003-01-09

申请人： Earl T. Cohen ,  Flavio Giovanni Bonomi

发明人： Earl T. Cohen ,  Flavio Giovanni Bonomi

IPC分类号： H04L12/26 ,  H04L12/56

CPC分类号： H04L47/6215 ,  H04L47/50 ,  H04L47/521 ,  H04L49/201 ,  H04L49/254 ,  H04L49/506 ,  H04L49/508 ,  H04Q2213/13003 ,  H04Q2213/13103 ,  H04Q2213/13242 ,  H04Q2213/1325 ,  H04Q2213/13296

摘要： Methods and apparatus are disclosed for simultaneously scheduling multiple priorities of packets, such as in systems having a non-blocking switching fabric. In one implementation, the maximum bandwidth which a particular input can send is identified. During a scheduling cycle, a current bandwidth desired for a first priority of traffic is identified, which leaves the remaining bandwidth available for a second priority of traffic without affecting the bandwidth allocated to the first priority of traffic. By determining these bandwidth amounts at each iteration of a scheduling cycle, multiple priorities of traffic can be simultaneously scheduled. This approach may be used by a wide variety of scheduling approaches, such as, but not limited to using a SLIP algorithm or variant thereof. When used in conjunction with a SLIP algorithm, the current desired bandwidths typically correspond to high and low priority requests.

摘要翻译： 公开了用于同时调度分组的多个优先级的方法和装置，例如在具有非阻塞交换结构的系统中。 在一个实现中，识别特定输入可以发送的最大带宽。 在调度周期期间，识别业务的第一优先级所期望的当前带宽，这使剩余带宽可用于业务的第二优先级，而不影响分配给业务的第一优先级的带宽。 通过在调度周期的每次迭代中确定这些带宽量，可以同时调度业务的多个优先级。 这种方法可以通过各种调度方法使用，诸如但不限于使用SLIP算法或其变体。 当与SLIP算法结合使用时，当前期望的带宽通常对应于高优先级请求和低优先级请求。

公开(公告)号：US07408937B1

公开(公告)日：2008-08-05

申请号：US10338985

申请日：2003-01-09

申请人： Earl T. Cohen ,  Tony Lee Werner

发明人： Earl T. Cohen ,  Tony Lee Werner

IPC分类号： H04L12/56

CPC分类号： H04L47/6255 ,  H04L47/50 ,  H04L47/522 ,  H04L2012/5679 ,  H04L2012/5681

摘要： Methods and apparatus are disclosed for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms, such as, but not limited to the SLIP/I SLIP scheduling algorithms or variants thereof. Each of the groups of items is typically identified with a number of items the group desires to be selected. Based on an identified starting position, a progressive sum value is initialized, with progressive sum values corresponding to successive groups of items in the sequence being adjusted typically based on the corresponding number of items each successive group desires to be selected. The number of items a particular group is authorized to select can then be determined, such as, but not limited to, by being based on its corresponding progressive sum value, the progressive sum value of the immediately prior group in the sequence, and its desired number of items to be selected.

摘要翻译： 公开了用于从可能由分组或其他调度机制特别有用的可变起始位置顺序地识别可变数量的项目的方法和装置，诸如但不限于SLIP / I SLIP调度算法或其变体。 每个项目组中的每一组通常用群组希望选择的项目来标识。 基于所识别的开始位置，初始化渐进和值，其中对应于序列中的连续组的项目的渐进和值通常基于每个连续组期望选择的对应数量来调整。 然后可以确定特定组被授权选择的项目的数量，例如但不限于通过基于其对应的渐进和值，序列中紧前的组的渐进和值和其期望的 要选择的项目数量

公开(公告)号：US07349418B1

公开(公告)日：2008-03-25

申请号：US10617539

申请日：2003-07-11

申请人： Earl T. Cohen

发明人： Earl T. Cohen

IPC分类号： H04L12/28 ,  H04L12/56 ,  G01R31/08 ,  G06F11/00

CPC分类号： H04L47/10 ,  H04L47/30 ,  H04L47/365 ,  H04L49/90 ,  H04L49/9084 ,  H04L49/9094

摘要： Processing a packet typically includes enqueuing the packet on to a queue when it arrives at a device, and then at some later time under control of the scheduler, dequeuing the packet for transmission. The scheduler needs some representation of the packet length for its uses when dequeuing. By storing the packet length as an adjusted packet length containing fewer bits, the scheduler and any storage of the packets lengths in the queues are reduced in complexity/size. One implementation maintains a residue amount corresponding to one or more packet queues or streams of packets. The residue amount is updated to maintain a forward looking or lagging behind indication of the error induced by this approximation. An adjusted packet length for the packet is determined based on its actual packet length and the residue amount. The residue amount is accordingly updated to reduce any long term error induced by using the adjusted packet lengths.

摘要翻译： 处理数据包通常包括：当数据包到达某个设备时将数据包加入到队列中，然后在调度程序的控制下稍后的一段时间将该数据包出队进行传输。 调度程序需要在出队时使用其数据包长度的一些表示。 通过将分组长度存储为包含较少比特的调整分组长度，调度器和队列中的分组长度的任何存储器的复杂度/大小都被减少。 一个实现保持对应于一个或多个分组队列或分组流的残留量。 残留量被更新以保持由该近似引起的误差的向前看或滞后的指示。 基于其实际分组长度和剩余量确定分组的经调整分组长度。 因此，残留量被更新以减少通过使用调整的分组长度而引起的任何长期误差。

公开(公告)号：US07080365B2

公开(公告)日：2006-07-18

申请号：US10113582

申请日：2002-03-29

申请人： Jeffrey M. Broughton ,  Liang T. Chen ,  William kwei-cheung Lam ,  Derek E. Pappas ,  Ihao Chen ,  Thomas M. McWilliams ,  Ankur Narang ,  Jeffrey B. Rubin ,  Earl T. Cohen ,  Michael W. Parkin ,  Ashley N. Saulsbury ,  Michael S. Ball

发明人： Jeffrey M. Broughton ,  Liang T. Chen ,  William kwei-cheung Lam ,  Derek E. Pappas ,  Ihao Chen ,  Thomas M. McWilliams ,  Ankur Narang ,  Jeffrey B. Rubin ,  Earl T. Cohen ,  Michael W. Parkin ,  Ashley N. Saulsbury ,  Michael S. Ball

IPC分类号： G06F9/45

CPC分类号： G06F17/5022 ,  G06F8/427 ,  G06F8/443 ,  G06F8/445 ,  G06F8/45

摘要： A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

公开(公告)号：US06556045B2

公开(公告)日：2003-04-29

申请号：US09826563

申请日：2001-04-04

申请人： Earl T. Cohen

发明人： Earl T. Cohen

IPC分类号： G06F738

CPC分类号： G06F17/5045 ,  G11C7/1039 ,  G11C7/1072

摘要： A system and method for designing a digital circuit. The method includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circuit. Each copy of the single phase circuit is a phase and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The method includes identifying the state devices within the single phase digital circuit, replacing each state device in the single phase digital circuit with a multiphase state saving device and providing control signals to each multiphase state saving device to control the reading and writing of state information for each phase into and out of a respective multiphase state saving device.