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    Contact structure for memory device
    71.
    发明授权
    Contact structure for memory device 失效
    存储器件的接触结构

    公开(公告)号：US06229174B1

    公开(公告)日：2001-05-08

    申请号：US08986897

    申请日：1997-12-08

    申请人： Kunal R. Parekh

    发明人： Kunal R. Parekh

    IPC分类号： H01L27108

    CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76882 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10888

    摘要： Disclosed is a method of forming a self-aligned contact to a semiconductor substrate by use of a sacrificial spacer. The sacrificial spacer has the advantage of self aligning metallization to the semiconductive substrate or to a polysilicon plug material without extra photolithography steps as are required in the prior art.

    摘要翻译： 公开了通过使用牺牲间隔物形成与半导体衬底的自对准接触的方法。 牺牲间隔物具有如下优点，即在现有技术中需要的不需要额外的光刻步骤的情况下，将金属化自对准至半导体衬底或多晶硅插塞材料。

    SEMICONDUCTOR CONSTRUCTIONS
    72.
    发明申请
    SEMICONDUCTOR CONSTRUCTIONS 有权
    半导体构造

    公开(公告)号：US20130341725A1

    公开(公告)日：2013-12-26

    申请号：US14010444

    申请日：2013-08-26

    申请人： Kunal R. Parekh

    发明人： Kunal R. Parekh

    IPC分类号： H01L29/78 ,  H01L29/06

    CPC分类号： H01L29/78 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/0603 ,  H01L29/7841

    摘要： Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include OCIT memory having transistor gates entirely over SOI, and methods of forming such OCIT memory.

    摘要翻译： 一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。 一些实施例包括具有完全在SOI上的晶体管栅极的OCIT存储器，以及形成这种OCIT存储器的方法。

    Methods of forming memory arrays and semiconductor constructions
    73.
    发明授权
    Methods of forming memory arrays and semiconductor constructions 有权
    形成记忆阵列和半导体结构的方法

    公开(公告)号：US08530288B2

    公开(公告)日：2013-09-10

    申请号：US13612692

    申请日：2012-09-12

    申请人： Kunal R. Parekh

    发明人： Kunal R. Parekh

    IPC分类号： H01L21/00 ,  H01L27/108

    CPC分类号： H01L29/78 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/0603 ,  H01L29/7841

    摘要： Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

    摘要翻译： 一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。 一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种0C1T存储器的方法。

    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
    74.
    发明授权
    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates 有权
    形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，包括晶体管栅极阵列和门阵列外围的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极和第二接地 隔离门

    公开(公告)号：US08389363B2

    公开(公告)日：2013-03-05

    申请号：US13017508

    申请日：2011-01-31

    申请人： Young Pil Kim ,  Kunal R. Parekh

    发明人： Young Pil Kim ,  Kunal R. Parekh

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管门阵列和门阵列的外围电路，以及形成集成电路的方法，该集成电路包括晶体管门阵列，其包括第一栅极 和第二接地隔离门。 在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。 通过掩模材料形成沟槽并进入半导体材料。 栅介电材料形成在半导体材料的沟槽内。 栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。 形成源/漏区。 考虑了其他方面和实现。

    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
    77.
    发明授权
    Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates 有权
    形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，包括晶体管栅极阵列和门阵列外围的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极和第二接地 隔离门

    公开(公告)号：US07700441B2

    公开(公告)日：2010-04-20

    申请号：US11346914

    申请日：2006-02-02

    申请人： Young Pil Kim ,  Kunal R. Parekh

    发明人： Young Pil Kim ,  Kunal R. Parekh

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管栅极阵列和外围于栅极阵列的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极 和第二接地隔离门。 在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。 通过掩模材料形成沟槽并进入半导体材料。 栅介电材料形成在半导体材料的沟槽内。 栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。 形成源/漏区。 考虑了其他方面和实现。

    Methods of forming memory circuitry
    79.
    发明授权
    Methods of forming memory circuitry 有权
    形成存储器电路的方法

    公开(公告)号：US07462534B2

    公开(公告)日：2008-12-09

    申请号：US11196051

    申请日：2005-08-02

    申请人： Kunal R. Parekh ,  Suraj Mathew ,  Steve Cole

    发明人： Kunal R. Parekh ,  Suraj Mathew ,  Steve Cole

    IPC分类号： H01L21/8244

    CPC分类号： H01L29/6656 ,  H01L27/10882 ,  H01L27/10891 ,  H01L27/10894

    摘要： The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成存储器电路的方法。 在一个实现中，提供了具有存储器阵列电路区域和外围电路区域的衬底。 存储器阵列电路区域包括具有第一最小线间距的晶体管栅极线。 外围电路区域包括具有大于第一最小线间距的第二最小线间距的晶体管栅极线。 在存储器阵列区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物之前，在外围电路区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物。 考虑了其他方面和实现。