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    Non-volatile memory cells and methods of manufacturing the same
    71.
    发明授权
    Non-volatile memory cells and methods of manufacturing the same 有权
    非易失性存储单元及其制造方法

    公开(公告)号：US07468299B2

    公开(公告)日：2008-12-23

    申请号：US11197659

    申请日：2005-08-04

    Applicant: ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.

    Abstract translation: 用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质 材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

    Method of manufacturing a non-volatile memory device
    72.
    发明授权
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US07414282B2

    公开(公告)日：2008-08-19

    申请号：US11203087

    申请日：2005-08-15

    Applicant: Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    Abstract translation: 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Dual gate multi-bit semiconductor memory array
    75.
    发明申请
    Dual gate multi-bit semiconductor memory array 有权
    双门多位半导体存储器阵列

    公开(公告)号：US20070194365A1

    公开(公告)日：2007-08-23

    申请号：US11356659

    申请日：2006-02-17

    Applicant: ChiaHua Ho ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Hang-Ting Lue

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: An array of memory cells is arranged in columns and one or more rows on a semiconductor substrate. Each cell has a source, a drain, a first gate and a second gate. The array includes a plurality of gate control lines, each of which corresponds to one of the columns of the memory cells, where each control line connects to the first gate of the memory cell in the corresponding column in each of the rows; and one or more word lines, each of which corresponds to one of the rows of the memory cells, where each word line connects to the second gate of each of the cells in the corresponding row.

    Abstract translation: 存储单元阵列布置成半导体衬底上的一列或多行。 每个单元具有源极，漏极，第一栅极和第二栅极。 阵列包括多个栅极控制线，每条栅极控制线对应于存储器单元的列之一，其中每个控制线连接到每行的相应列中的存储单元的第一栅极; 以及一个或多个字线，每个字线对应于存储器单元的行之一，其中每个字线连接到相应行中每个单元的第二个栅极。

    Memory device
    76.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US07259995B2

    公开(公告)日：2007-08-21

    申请号：US11016666

    申请日：2004-12-17

    Applicant: Yen-Hao Shih ,  Hang-Ting Lue

    Inventor： Yen-Hao Shih ,  Hang-Ting Lue

    IPC: G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/3418

    Abstract: A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a transistor control gate and a transistor channel region. The method further comprises applying a negative voltage bias to the transistor control gate. In another embodiment, the method further comprises performing a baking process on the memory device. The method further comprises performing a memory operation on the memory device.

    Abstract translation: 稳定存储器件的方法包括在存储器件的电荷俘获层中俘获多个电荷。 电荷捕获层位于晶体管控制栅极和晶体管沟道区域之间。 该方法还包括向晶体管控制栅极施加负电压偏置。 在另一个实施例中，该方法还包括在存储器件上执行烘焙处理。 该方法还包括对存储器设备执行存储器操作。

    Asymmetric floating gate nand flash memory
    77.
    发明申请
    Asymmetric floating gate nand flash memory 有权
    非对称浮栅nand闪存

    公开(公告)号：US20070090442A1

    公开(公告)日：2007-04-26

    申请号：US11209437

    申请日：2005-08-23

    Applicant: Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Hsieh

    Inventor： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Hsieh

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521

    Abstract: A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

    Abstract translation: NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。 给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。 因此，浮置栅极下的反相通道可以作为源极/漏极。 结果，存储器件不需要浅结或辅助栅。 此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。

    Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
    78.
    发明申请
    Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays 审中-公开

    公开(公告)号：US20060198189A1

    公开(公告)日：2006-09-07

    申请号：US11324495

    申请日：2006-01-03

    Applicant: Hang-Ting Lue ,  Sheng-Chih Lai

    Inventor： Hang-Ting Lue ,  Sheng-Chih Lai

    IPC: G11C16/04

    CPC classification number: G11C16/349

    Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

    Method for controlling current during read and program operations of programmable diode
    80.
    发明授权
    Method for controlling current during read and program operations of programmable diode 有权
    用于在可编程二极管的读取和编程操作期间控制电流的方法

    公开(公告)号：US07088613B2

    公开(公告)日：2006-08-08

    申请号：US10846006

    申请日：2004-05-14

    Applicant: Hang-Ting Lue ,  Ming-Hsiu Lee

    Inventor： Hang-Ting Lue ,  Ming-Hsiu Lee

    IPC: G11C11/36

    CPC classification number: G11C5/147

    Abstract: A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.

    Abstract translation: 提供了一种用于在存储器结构中的读取和编程操作期间控制电流波动的方法。 该方法包括将第一电压施加到字线解码晶体管的第一栅极。 该方法还包括将第二电压施加到位线解码晶体管的第二栅极，使得第一电压大于第二电压。 该方法还包括将位线解码晶体管的源电压保持在大约零。

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