公开(公告)号：US08426294B2

公开(公告)日：2013-04-23

申请号：US13476964

申请日：2012-05-21

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

IPC分类号： H01L29/76

CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US07088613B2

公开(公告)日：2006-08-08

申请号：US10846006

申请日：2004-05-14

申请人： Hang-Ting Lue ,  Ming-Hsiu Lee

发明人： Hang-Ting Lue ,  Ming-Hsiu Lee

IPC分类号： G11C11/36

CPC分类号： G11C5/147

摘要： A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.

摘要翻译： 提供了一种用于在存储器结构中的读取和编程操作期间控制电流波动的方法。 该方法包括将第一电压施加到字线解码晶体管的第一栅极。 该方法还包括将第二电压施加到位线解码晶体管的第二栅极，使得第一电压大于第二电压。 该方法还包括将位线解码晶体管的源电压保持在大约零。

公开(公告)号：US07209390B2

公开(公告)日：2007-04-24

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C16/00

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。 通过这些再填充循环可以大大提高电荷保持性。

公开(公告)号：US20050237816A1

公开(公告)日：2005-10-27

申请号：US10876378

申请日：2004-06-24

申请人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

发明人： Hang-Ting Lue ,  Yen-Hao Shih ,  Kuang Yeu Hsieh ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC分类号： G11C11/36 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3481 ,  G11C16/0466 ,  G11C16/3436

摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.

摘要翻译： 具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。 充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。 该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

公开(公告)号：US20050254296A1

公开(公告)日：2005-11-17

申请号：US10846006

申请日：2004-05-14

申请人： Hang-Ting Lue ,  Ming-Hsiu Lee

发明人： Hang-Ting Lue ,  Ming-Hsiu Lee

IPC分类号： G11C5/14 ,  G11C11/36

CPC分类号： G11C5/147

摘要： A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.

摘要翻译： 提供了一种用于在存储器结构中的读取和编程操作期间控制电流波动的方法。 该方法包括将第一电压施加到字线解码晶体管的第一栅极。 该方法还包括将第二电压施加到位线解码晶体管的第二栅极，使得第一电压大于第二电压。 该方法还包括将位线解码晶体管的源电压保持在大约零。

公开(公告)号：US08437192B2

公开(公告)日：2013-05-07

申请号：US12785291

申请日：2010-05-21

申请人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

发明人： Hsiang-Lan Lung ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Tien-Yen Wang

IPC分类号： G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C5/02 ,  G11C5/06

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。 包括导电材料层的共同源平面位于顶部和底部存储立方体之间。 源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。 通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

公开(公告)号：US09019771B2

公开(公告)日：2015-04-28

申请号：US13661723

申请日：2012-10-26

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0475 ,  G11C16/10

摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

摘要翻译： 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

公开(公告)号：US09000412B2

公开(公告)日：2015-04-07

申请号：US13561558

申请日：2012-07-30

申请人： Wei-Chih Chien ,  Feng-Ming Lee ,  Ming-Hsiu Lee

发明人： Wei-Chih Chien ,  Feng-Ming Lee ,  Ming-Hsiu Lee

IPC分类号： H01L29/06 ,  G11C13/00 ,  H01L43/02 ,  H01L45/00

CPC分类号： G11C13/0002 ,  G11C13/003 ,  H01L27/2409 ,  H01L43/02 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

摘要： A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

摘要翻译： 提供了一种切换装置及其操作方法及其存储器阵列。 开关装置包括第一固体电解质，第二固体电解质和开关层。 开关层与第一固体电解质和第二固体电解质相邻。

公开(公告)号：US08937291B2

公开(公告)日：2015-01-20

申请号：US13528754

申请日：2012-06-20

申请人： Ming-Hsiu Lee ,  Wei-Chih Chien

发明人： Ming-Hsiu Lee ,  Wei-Chih Chien

IPC分类号： H01L47/00 ,  H01L29/06

CPC分类号： H01L27/0688 ,  H01L27/101 ,  H01L27/1022

摘要： A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.

摘要翻译： 所公开的存储器件包括三维阵列结构，其包括设置在存储层之间的存储层和晶体管结构。 每个存储器层连接到公共电极，并且每个晶体管结构包括共享公共列结构和公共基极结构的晶体管。 晶体管还各自包括通过公共基底结构与公共柱结构间隔开的连接器结构。

公开(公告)号：US08824188B2

公开(公告)日：2014-09-02

申请号：US13567750

申请日：2012-08-06

申请人： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

发明人： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/77

摘要： An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

摘要翻译： 提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。 存储器件的操作方法包括以下步骤。 使存储器件处于置位状态。 用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。 读取设置状态的存储器件。 一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。 将恢复的偏置电压施加到存储器件。 在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。