公开(公告)号：US06815803B1

公开(公告)日：2004-11-09

申请号：US09596129

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06799290B1

公开(公告)日：2004-09-28

申请号：US09512756

申请日：2000-02-25

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  David Russell Hanson

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  David Russell Hanson

IPC分类号： G11C2900

CPC分类号： G11C29/02

摘要： A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.

摘要翻译： 根据本发明的用于测试半导体存储器件的数据路径的方法包括提供包括数据路径中的多个级并将数据传送到数据路径的半导体存储器件。 组件被禁用以隔离多个级中的至少一个级，使得写入或从至少一个级读取的数据在输出端可用。 优选地将输出端的数据与预期数据进行比较。 或者，可以执行设备之间的系统级校准，以确保设备之间的正确通信，而不会破坏存储器阵列中的数据并且在运行应用时可能进行动态数据偏移校准。

公开(公告)号：US06680857B2

公开(公告)日：2004-01-20

申请号：US09964208

申请日：2001-09-26

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： H01L27020

CPC分类号： G11C29/70

摘要： Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.

摘要翻译： 在电路元件和逻辑块之间的电路部分提供多个导电路径，能够修复在不使用熔断的情况下连接电路元件和逻辑块的导线中的缺陷。

公开(公告)号：US06668031B1

公开(公告)日：2003-12-23

申请号：US09377588

申请日：1999-08-19

申请人： David Russell Hanson ,  Gerhard Mueller

发明人： David Russell Hanson ,  Gerhard Mueller

IPC分类号： H04L700

CPC分类号： G11C7/1078 ,  H04L7/0008

摘要： A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal. The data clocking circuit outputs a synchronized capture data signal having the first voltage level higher than the reduced voltage level.

摘要翻译： 一种同步数据捕获电路，被配置为将数据信号中的数据的捕获与集成电路中的定时信号同步。 同步数据电路采用具有降低的电压电平的电压信号，数据信号和定时信号具有高于降低的电压电平的第一电压电平。 同步数据捕获电路包括布置成接收定时信号的定时驱动器电路。 定时驱动器电路输出具有降低的电压电平的降低电压定时信号。 包括数据驱动器电路，其布置成接收数据信号和定时信号，数据驱动器输出具有降低的电压电平的降低电压的时钟数据信号。 还包括耦合到定时驱动器电路和数据驱动器电路的数据时钟电路。 数据时钟电路被布置为接收降低的电压定时信号和降低的电压时钟数据信号。 数据时钟电路输出具有高于降低的电压电平的第一电压电平的同步捕获数据信号。

公开(公告)号：US06522171B2

公开(公告)日：2003-02-18

申请号：US09759011

申请日：2001-01-11

申请人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

发明人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

IPC分类号： H03K19096

CPC分类号： H03K19/0016 ,  H03K19/0963

摘要： A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

公开(公告)号：US06469392B2

公开(公告)日：2002-10-22

申请号：US09751492

申请日：2000-12-28

申请人： Young-Jin Park ,  Gerhard Mueller

发明人： Young-Jin Park ,  Gerhard Mueller

IPC分类号： H01L23528

CPC分类号： H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit having conductive lines with non-rectangular shaped cross-sections. The non-rectangular shaped cross-sections facilitate a reduction in line pitch without increasing capacitive coupling noise between adjacent conductive lines or, alternatively, reduction in capacitive coupling noise between adjacent lines for a given pitch.

摘要翻译： 一种具有非矩形横截面的导线的集成电路。 非矩形横截面有助于减小线间距，而不会增加相邻导线之间的电容耦合噪声，或者替代地，减小给定间距的相邻线之间的电容耦合噪声。

公开(公告)号：US06327170B1

公开(公告)日：2001-12-04

申请号：US09406890

申请日：1999-09-28

申请人： Gerhard Mueller ,  Ulrike Gruening

发明人： Gerhard Mueller ,  Ulrike Gruening

IPC分类号： G11C508

CPC分类号： G11C11/4097

摘要： An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number≧1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number≠m. The vertical-horizontal twists transform coupling noise into common mode noise.

摘要翻译： 描述了包括第一和第二位线对410和420的集成电路。 位线对的位线路径位于不同的位线上。 处于不同位线电平的第一和第二位线对的位线路径彼此相邻。 第一位线对包括m垂直水平扭转440，其中m是整数> = 1，第二位线对包括n个垂直 - 水平扭转460和461，其中n是整数m。 垂直水平扭转将耦合噪声转换为共模噪声。

公开(公告)号：US06313663B1

公开(公告)日：2001-11-06

申请号：US09491635

申请日：2000-01-27

申请人： Gerhard Mueller ,  David R. Hanson

发明人： Gerhard Mueller ,  David R. Hanson

IPC分类号： H03K190185

CPC分类号： B24B9/065 ,  B24B37/04 ,  G11C5/063 ,  H03K19/0013 ,  H03K19/018592 ,  H03K19/09429

摘要： A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line. The second full-swing unidirectional repeater circuit is configured to pass a second full swing signal from the second portion of the signal line to the first portion of the signal line when the second enable signal is enabled, wherein the first full-swing unidirectional repeater circuit and the second full-swing unidirectional repeater circuit are tri-stated when both the first enable signal and the second enable signal are disabled.

摘要翻译： 在集成电路的信号线上实现的双向全摆幅电压中继器，其包括用于提供第一使能信号的第一使能节点和用于提供第二使能信号的第二使能节点。 包括耦合在信号线的第一部分和信号线的第二部分之间的第一全方位单向中继器电路。 第一全方位单向中继器被配置为当第一使能信号被使能时，将第一全摆幅信号从信号线的第一部分传递到信号线的第二部分。 第二全方位单向中继器电路耦合在信号线的第一部分和信号线的第二部分之间。 第二全方位单向中继器电路被配置为当第二使能信号被使能时，将第二全摆幅信号从信号线的第二部分传递到信号线的第一部分，其中第一全方位单向中继器电路 而当第一使能信号和第二使能信号都被禁止时，第二全方位单向中继器电路是三态的。

公开(公告)号：US06307397B1

公开(公告)日：2001-10-23

申请号：US09491646

申请日：2000-01-27

申请人： Gerhard Mueller ,  David R. Hanson

发明人： Gerhard Mueller ,  David R. Hanson

IPC分类号： H03K1902

CPC分类号： B24B9/065 ,  B24B37/04 ,  G11C5/063 ,  H03K19/0013 ,  H03K19/018592 ,  H03K19/09429

摘要： A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.

摘要翻译： 一种用于在其上具有减小的电压信号的信号线上实现减小电压中继器电路的集成电路中的方法。 降低的电压信号的电压电平低于VDD。 减小电压中继器电路被配置为耦合到信号线并且具有耦合到信号线的第一部分的输入节点，用于接收第一降低电压信号和耦合到信号线的第二部分的输出节点，用于输出 第二降压信号。 该方法包括将输入节点耦合到信号线的第一部分。 输入节点耦合到减电压中继器电路的输入级。 输入级被配置为在信号线上接收第一降低电压信号。 输入级还耦合到电平移位器级，电平移位器级被布置成响应于第一降低电压信号输出一组电平移位器级控制信号。 电平移位器级控制信号的电压范围高于与第一降压信号相关联的电压范围。 还包括将输出节点耦合到信号线的第二部分。 输出节点也耦合到减电压中继器电路的输出级。 输出级被配置为响应于电平移位器级控制信号的集合而在输出节点上输出第二降压信号。 第二降压信号的电压范围低于电平移位器级控制信号的电压范围。

公开(公告)号：US06291335B1

公开(公告)日：2001-09-18

申请号：US09411551

申请日：1999-10-04

申请人： Rainer Florian Schnabel ,  Ulrike Gruening ,  Thomas Rupp ,  Gerhard Mueller

发明人： Rainer Florian Schnabel ,  Ulrike Gruening ,  Thomas Rupp ,  Gerhard Mueller

IPC分类号： H01L214763

CPC分类号： H01L27/10885 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/28525 ,  H01L21/76807 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10888 ,  H01L27/10894

摘要： A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

摘要翻译： 根据本发明的用于制造具有由三个接触电平组成的分裂电平折叠位线结构的半导体存储器的方法包括在阵列区域和衬底的支撑区域中形成用于晶体管的栅极结构。 第一触点形成在阵列区域中的栅极结构之间的扩散区域。 第一触点具有与阵列区域中的所有第一触点基本相同的高度。 在阵列区域的第一级位线和第一触点的第一部分之间形成第二触点，同时从支撑区域中的栅极结构和扩散区域形成第二触点到第一金属层。 在支撑区域中从第一金属层形成与第二金属层形成第三触点的第三触点形成在阵列区域中的第二电平位线和第一触点的第二部分之间。