公开(公告)号：US20080074941A1

公开(公告)日：2008-03-27

申请号：US11938756

申请日：2007-11-12

申请人： Kazushige KANDA ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Tamio Ikehashi

发明人： Kazushige KANDA ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Tamio Ikehashi

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C17/18

摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.

摘要翻译： 本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路， 根据外部输入禁用第二电路。

公开(公告)号：US20060104112A1

公开(公告)日：2006-05-18

申请号：US11318524

申请日：2005-12-28

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

公开(公告)号：US06278639B1

公开(公告)日：2001-08-21

申请号：US09392127

申请日：1999-09-08

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Tamio Ikehashi ,  Kazushige Kanda ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Tamio Ikehashi ,  Kazushige Kanda ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C700

CPC分类号： G11C5/145

摘要： The booster circuit of the present invention includes a first booster cell section in which one or more booster cells are connected in series, and a second booster cell section having an end which is connected to the first booster cell section, in which a plurality of booster cell groups each containing one or more booster cells connected in series, are connected to each other in parallel.

摘要翻译： 本发明的升压电路包括其中一个或多个升压电池串联连接的第一升压电池部分和具有连接到第一升压电池部分的端部的第二升压电池部分，其中多个增压器 每个包含串联连接的一个或多个升压电池的电池组彼此并联连接。

公开(公告)号：US5680347A

公开(公告)日：1997-10-21

申请号：US496625

申请日：1995-06-29

申请人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

发明人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

IPC分类号： G11C7/12 ,  G11C16/04 ,  G11C16/28 ,  G11C11/40 ,  G11C17/00

CPC分类号： G11C16/0483 ,  G11C16/28 ,  G11C7/12

摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which a plurality of memory cell units are arranged in a matrix, and a first and second common signal lines for exchanging signals with the memory cell array, wherein each of the memory cell units contains a nonvolatile memory section having at least one nonvolatile memory cell, a first select MOS transistor for making the nonvolatile memory section conducting to the first common signal line, and a second select MOS transistor with a threshold voltage different from that of the first select MOS transistor for making the nonvolatile memory section conducting to the second common signal line.

摘要翻译： 非易失性半导体存储器件包括其中多个存储单元单元以矩阵形式布置的存储单元阵列，以及用于与存储单元阵列交换信号的第一和第二公共信号线，其中每个存储单元单元包含一个 具有至少一个非易失性存储单元的非易失性存储器部分，用于使非易失性存储器部分导通到第一公共信号线的第一选择MOS晶体管和具有与第一选择MOS晶体管不同的阈值电压的第二选择MOS晶体管， 使得非易失性存储器部分导通到第二公共信号线。

公开(公告)号：US5940321A

公开(公告)日：1999-08-17

申请号：US866350

申请日：1997-05-30

申请人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

发明人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

IPC分类号： G11C7/12 ,  G11C16/04 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C16/28 ,  G11C7/12

摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which a plurality of memory cell units are arranged in a matrix, and a first and second common signal lines for exchanging signals with the memory cell array, wherein each of the memory cell units contains a nonvolatile memory section having at least one nonvolatile memory cell, a first select MOS transistor for making the nonvolatile memory section conducting to the first common signal line, and a second select MOS transistor with a threshold voltage different from that of the first select MOS transistor for making the nonvolatile memory section conducting to the second common signal line.

公开(公告)号：US5698879A

公开(公告)日：1997-12-16

申请号：US516924

申请日：1995-08-18

申请人： Seiichi Aritome ,  Tomoharu Tanaka ,  Ken Takeuchi

发明人： Seiichi Aritome ,  Tomoharu Tanaka ,  Ken Takeuchi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory device has reduced parasitic capacitance at a select transistor obtained by providing a depletion-mode select transistor with a charge accumulation layer, virtually making a gate insulating film thicker, or providing under the gate insulating film a channel layer that is of a same conductivity type as that of a source and drain regions and connects thereto, thereby enabling the potential of the select gate to be almost fixed at a desired value, preventing a faulty operation and making it possible to cause the select transistor to operate at high speed.

摘要翻译： 非易失性半导体存储器件通过提供具有电荷累积层的耗尽型选择晶体管而获得的选择晶体管具有减小的寄生电容，实际上使栅极绝缘膜更厚，或者在栅极绝缘膜下方设置沟道层， 与源极和漏极区相同的导电类型并与其连接，从而使选择栅极的电位几乎固定在期望值，防止故障操作并且使得可以使选择晶体管以高速运行 。

公开(公告)号：US6046940A

公开(公告)日：2000-04-04

申请号：US295335

申请日：1999-04-21

申请人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

发明人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

IPC分类号： G11C7/12 ,  G11C16/04 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C16/28 ,  G11C7/12

摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which a plurality of memory cell units are arranged in a matrix, and a first and second common signal lines for exchanging signals with the memory cell array, wherein each of the memory cell units contains a nonvolatile memory section having at least one nonvolatile memory cell, a first select MOS transistor for making the nonvolatile memory section conducting to the first common signal line, and a second select MOS transistor with a threshold voltage different from that of the first select MOS transistor for making the nonvolatile memory section conducting to the second common signal line.

摘要翻译： 非易失性半导体存储器件包括其中多个存储单元单元以矩阵形式布置的存储单元阵列，以及用于与存储单元阵列交换信号的第一和第二公共信号线，其中每个存储单元单元包含一个 具有至少一个非易失性存储单元的非易失性存储器部分，用于使非易失性存储器部分导通到第一公共信号线的第一选择MOS晶体管和具有与第一选择MOS晶体管不同的阈值电压的第二选择MOS晶体管， 使得非易失性存储器部分导通到第二公共信号线。

公开(公告)号：US06674318B2

公开(公告)日：2004-01-06

申请号：US10231082

申请日：2002-08-30

申请人： Kazushige Kanda ,  Tamio Ikehashi ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Kazushige Kanda ,  Tamio Ikehashi ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G05F110

CPC分类号： G11C7/062

摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.

摘要翻译： 半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号 用于稳定第一外部端子的升压电压。 监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压 给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。 为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志 。 因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。

公开(公告)号：US06351179B1

公开(公告)日：2002-02-26

申请号：US09375370

申请日：1999-08-17

申请人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

发明人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

IPC分类号： G05F110

CPC分类号： G05F1/465

摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

摘要翻译： 为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止 通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。 此外，通过在待机模式中采用PMOS下变频器和在激活模式下的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置 处于待机模式的PMOS下变频器的内部电源电压高于活动模式。 下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离 电源电压最小化，内部电源电压的可控性提高。

公开(公告)号：US06590444B2

公开(公告)日：2003-07-08

申请号：US10200152

申请日：2002-07-23

申请人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

发明人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

IPC分类号： G05F302

CPC分类号： G05F1/465

摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

摘要翻译： 为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止 通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。 此外，通过在待机模式中采用PMOS下变频器和在活动模式中的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置 处于待机模式的PMOS下变频器的内部电源电压高于活动模式。 下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离 电源电压最小化，内部电源电压的可控性提高。