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    Nonvolatile semiconductor memory device
    1.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5680347A

    公开(公告)日：1997-10-21

    申请号：US496625

    申请日：1995-06-29

    申请人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

    发明人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

    IPC分类号： G11C7/12 ,  G11C16/04 ,  G11C16/28 ,  G11C11/40 ,  G11C17/00

    CPC分类号： G11C16/0483 ,  G11C16/28 ,  G11C7/12

    摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which a plurality of memory cell units are arranged in a matrix, and a first and second common signal lines for exchanging signals with the memory cell array, wherein each of the memory cell units contains a nonvolatile memory section having at least one nonvolatile memory cell, a first select MOS transistor for making the nonvolatile memory section conducting to the first common signal line, and a second select MOS transistor with a threshold voltage different from that of the first select MOS transistor for making the nonvolatile memory section conducting to the second common signal line.

    摘要翻译： 非易失性半导体存储器件包括其中多个存储单元单元以矩阵形式布置的存储单元阵列，以及用于与存储单元阵列交换信号的第一和第二公共信号线，其中每个存储单元单元包含一个 具有至少一个非易失性存储单元的非易失性存储器部分，用于使非易失性存储器部分导通到第一公共信号线的第一选择MOS晶体管和具有与第一选择MOS晶体管不同的阈值电压的第二选择MOS晶体管， 使得非易失性存储器部分导通到第二公共信号线。

    Nonvolatile semiconductor memory device
    3.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US6046940A

    公开(公告)日：2000-04-04

    申请号：US295335

    申请日：1999-04-21

    申请人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

    发明人： Ken Takeuchi ,  Koji Sakui ,  Tomoharu Tanaka ,  Seiichi Aritome

    IPC分类号： G11C7/12 ,  G11C16/04 ,  G11C16/28 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C16/28 ,  G11C7/12

    摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which a plurality of memory cell units are arranged in a matrix, and a first and second common signal lines for exchanging signals with the memory cell array, wherein each of the memory cell units contains a nonvolatile memory section having at least one nonvolatile memory cell, a first select MOS transistor for making the nonvolatile memory section conducting to the first common signal line, and a second select MOS transistor with a threshold voltage different from that of the first select MOS transistor for making the nonvolatile memory section conducting to the second common signal line.

    摘要翻译： 非易失性半导体存储器件包括其中多个存储单元单元以矩阵形式布置的存储单元阵列，以及用于与存储单元阵列交换信号的第一和第二公共信号线，其中每个存储单元单元包含一个 具有至少一个非易失性存储单元的非易失性存储器部分，用于使非易失性存储器部分导通到第一公共信号线的第一选择MOS晶体管和具有与第一选择MOS晶体管不同的阈值电压的第二选择MOS晶体管， 使得非易失性存储器部分导通到第二公共信号线。

    Nonvolatile semiconductor memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5698879A

    公开(公告)日：1997-12-16

    申请号：US516924

    申请日：1995-08-18

    申请人： Seiichi Aritome ,  Tomoharu Tanaka ,  Ken Takeuchi

    发明人： Seiichi Aritome ,  Tomoharu Tanaka ,  Ken Takeuchi

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile semiconductor memory device has reduced parasitic capacitance at a select transistor obtained by providing a depletion-mode select transistor with a charge accumulation layer, virtually making a gate insulating film thicker, or providing under the gate insulating film a channel layer that is of a same conductivity type as that of a source and drain regions and connects thereto, thereby enabling the potential of the select gate to be almost fixed at a desired value, preventing a faulty operation and making it possible to cause the select transistor to operate at high speed.

    摘要翻译： 非易失性半导体存储器件通过提供具有电荷累积层的耗尽型选择晶体管而获得的选择晶体管具有减小的寄生电容，实际上使栅极绝缘膜更厚，或者在栅极绝缘膜下方设置沟道层， 与源极和漏极区相同的导电类型并与其连接，从而使选择栅极的电位几乎固定在期望值，防止故障操作并且使得可以使选择晶体管以高速运行 。

    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels
    9.
    发明授权
    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
    具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平

    公开(公告)号：US5321699A

    公开(公告)日：1994-06-14

    申请号：US851286

    申请日：1992-03-12

    申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

    摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

    摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。