公开(公告)号：US08306245B2

公开(公告)日：2012-11-06

申请号：US12125448

申请日：2008-05-22

申请人： Zining Wu

发明人： Zining Wu

IPC分类号： H03F99/00

CPC分类号： H03H17/0294 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/351 ,  H03H17/06 ,  H03H2220/08

摘要： A multimode audio amplifier comprises: a mode controller adapted to provide a control signal; and at least one multimode module, wherein each of the multimode modules has a plurality of operating modes, wherein the operating modes are selected in accordance with the control signal, wherein changing the operating modes results in a measurable change in at least one characteristic of the multimode audio amplifier; wherein the characteristics of the multimode audio amplifier consist of signal to noise ratio (SNR); total harmonic distortion and noise (THD+N); input to output delay; power consumption; and efficiency.

摘要翻译： 多模音频放大器包括：模式控制器，适于提供控制信号; 以及至少一个多模块模块，其中每个多模模块具有多个操作模式，其中根据控制信号选择操作模式，其中改变操作模式导致至少一个特征的可测量的变化 多模音频放大器; 其中多模音频放大器的特性由信噪比（SNR）组成; 总谐波失真和噪声（THD + N）; 输入到输出延迟; 能量消耗; 和效率。

公开(公告)号：US20120278682A1

公开(公告)日：2012-11-01

申请号：US13459013

申请日：2012-04-27

申请人： Xueshi Yang ,  Zining Wu

发明人： Xueshi Yang ,  Zining Wu

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048

摘要： Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.

摘要翻译： 自适应系统包括包括多个存储器单元的存储器件，数据质量监控块和自适应数据编码块，数据质量监控块和自适应数据编码块均可操作地耦合到存储器件。 数据质量监控块被配置为确定存储器件中包括的一个或多个存储器单元的组的质量值，所确定的质量值指示一个或多个存储器单元的组的质量。 自适应数据编码块被配置为从多个编码方案中选择编码方案来编码要写入存储器件中的一个或多个存储器单元的组的数据，编码方案的选择至少部分地基于 关于所确定的一个或多个存储单元组的质量值。

公开(公告)号：US20120233524A1

公开(公告)日：2012-09-13

申请号：US13475848

申请日：2012-05-18

申请人： Nedeljko Varnica ,  Seo-How Low ,  Gregory Burd ,  Zining Wu

发明人： Nedeljko Varnica ,  Seo-How Low ,  Gregory Burd ,  Zining Wu

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/116 ,  G11B20/1833 ,  G11B2020/185 ,  G11B2220/2504 ,  G11B2220/2508 ,  H03M13/036 ,  H03M13/6516

摘要： Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.

摘要翻译： 提供了构建用于全息存储的低密度奇偶校验码的系统和方法。 所述方法包括选择低密度奇偶校验码的参数，确定伴随的解码器中的比特处理元素的数量和存储量，以及构造准循环奇偶校验矩阵的母矩阵表示。 针对性能，内存考虑和吞吐量优化了低密度奇偶校验码。

公开(公告)号：US08219894B2

公开(公告)日：2012-07-10

申请号：US12324285

申请日：2008-11-26

申请人： Siu-Hung Fred Au ,  Gregory Burd ,  Zining Wu ,  Jun Xu ,  Ichiro Kikuchi ,  Tony Yoon

发明人： Siu-Hung Fred Au ,  Gregory Burd ,  Zining Wu ,  Jun Xu ,  Ichiro Kikuchi ,  Tony Yoon

IPC分类号： H03M13/00

CPC分类号： H03M13/458 ,  H03M13/098 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/1555 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/4146 ,  H03M13/45 ,  H03M13/451 ,  H03M13/63 ,  H03M13/6511

摘要： Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

摘要翻译： 提供系统和方法来实现里德 - 所罗门（RS）纠错系统的各个方面。 检测器可以从信道提供判决码字，并且还可以为判决码字提供软信息。 如果判决码字对应于内码，RS码是外码，则软信息映射可以处理用于判决码字的软信息以产生用于RS判决码字的软信息。 RS解码器可以使用Berlekamp-Massey算法（BMA），列表解码和Chien搜索，并且可以包括流水线架构。 可以使用基于阈值的控制电路来预测是否需要列表解码，并且如果它预测不需要列表解码，则可以暂停列表解码操作。

公开(公告)号：US08219886B1

公开(公告)日：2012-07-10

申请号：US11614868

申请日：2006-12-21

申请人： Pantas Sutardja ,  Zining Wu ,  Toai Doan ,  Aditya Ramamoorthy

发明人： Pantas Sutardja ,  Zining Wu ,  Toai Doan ,  Aditya Ramamoorthy

IPC分类号： G06F11/00

CPC分类号： G06F11/1072 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2029/0411

摘要： Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.

摘要翻译： 本发明的实施例提供了高密度，多级存储器。 因此，本发明的各种实施例提供了根据本发明的各种实施例的存储器装置，其包括包括多个单元的存储器块，每个单元适于用多电平信号进行操作。 这种存储装置还包括适于根据有利地实现多电平信号的多电平分布的编码方案对数据值进行编码的信道块，并且输出编码数据的相应多电平信号 值到内存块。 可以描述和要求保护其他实施例。

公开(公告)号：US08190963B1

公开(公告)日：2012-05-29

申请号：US12127669

申请日：2008-05-27

申请人： Zining Wu ,  Gregory Burd

发明人： Zining Wu ,  Gregory Burd

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/451

摘要： A method includes receiving a detected sequence representing a signal on a channel. The detected sequence includes data bits and one or more error detection code bits. One or more error indications are received for the detected sequence. Each of the one or more error indications identifies one of the data bits of the detected sequence that may have an erroneous value. Errors are detected in the detected sequence based on the error detection code bits in the detected sequence. When errors are detected in the detected sequence, a candidate sequence is generated based on the detected sequence and the one or more error indications.

摘要翻译： 一种方法包括接收表示信道上的信号的检测到的序列。 所检测的序列包括数据位和一个或多个错误检测码位。 为检测到的序列接收一个或多个错误指示。 一个或多个错误指示中的每一个标识可能具有错误值的检测到的序列的数据位之一。 基于检测到的序列中的错误检测码位，检测到的序列中检测到错误。 当在检测到的序列中检测到错误时，基于检测到的序列和一个或多个错误指示产生候选序列。

公开(公告)号：US08171380B2

公开(公告)日：2012-05-01

申请号：US11867858

申请日：2007-10-05

申请人： Xueshi Yang ,  Zining Wu

发明人： Xueshi Yang ,  Zining Wu

IPC分类号： H03M13/00

CPC分类号： G06F11/1048

摘要： Adaptive systems and methods that may help assure the reliability of data retrieved from memory cells are described herein. The systems may include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block may be configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block may be configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.

摘要翻译： 这里描述了可能有助于确保从存储器单元检索的数据的可靠性的自适应系统和方法。 系统可以包括包括多个存储器单元，数据质量监控块和自适应数据编码块的存储器件，数据质量监控块和自适应数据编码块都可操作地耦合到存储器件。 数据质量监测块可以被配置为确定存储器件中包括的一个或多个存储器单元的组的质量值，所确定的质量值指示一个或多个存储器单元的组的质量。 自适应数据编码块可以被配置为从多个编码方案中选择编码方案来编码要写入存储器件中的一个或多个存储器单元的组的数据，编码方案的选择至少基于 部分是确定的一个或多个存储单元的组的质量值。

公开(公告)号：US08144510B1

公开(公告)日：2012-03-27

申请号：US12404570

申请日：2009-03-16

申请人： Xueshi Yang ,  Zining Wu

发明人： Xueshi Yang ,  Zining Wu

IPC分类号： G11C11/34

CPC分类号： G11C11/5628

摘要： In a multi-level memory cell, when data to be programmed arrives, the cell is programmed to the lowest-charge state in which any bit position that is being programmed or has already been programmed has the correct value, regardless of the value in that state of any bit position that has not yet been programmed and is not being programmed. The programming of other bit positions based on subsequently arriving data should not then require a transition to an impermissible lower energy state. Although this may result in a transient condition in which some bits have the wrong value, by the time programming is complete, all bits would be expected to have the correct value. A cell may contain any number of bits equal to or greater than two, and programming may be performed cyclically (e.g., from LSB to MSB), anticyclically (e.g., from MSB to LSB), or in any random order.

摘要翻译： 在多级存储器单元中，当要编程的数据到达时，单元被编程为最低充电状态，其中正被编程或已被编程的任何位位置具有正确的值，而不管其值如何 任何尚未编程且未被编程的位位置的状态。 基于随后到达的数据的其他位位置的编程不应该需要转换到不允许的较低能量状态。 尽管这可能导致某些位具有错误值的瞬态条件，但在编程完成时，所有位将被预期具有正确的值。 单元可以包含等于或大于2的任何数量的位，并且可以循环（例如，从LSB到MSB），反周期地（例如，从MSB到LSB）或以任何随机顺序执行编程。

公开(公告)号：US08040953B2

公开(公告)日：2011-10-18

申请号：US11524789

申请日：2006-09-20

申请人： Shaohua Yang ,  Seo-How Low ,  Zining Wu ,  Gregory Burd

发明人： Shaohua Yang ,  Seo-How Low ,  Zining Wu ,  Gregory Burd

IPC分类号： H04N11/04 ,  G06K9/00 ,  H03M13/03

CPC分类号： H03M13/4153 ,  H03M13/098 ,  H03M13/2933 ,  H04L25/03203 ,  H04L25/067

摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology computes soft reliability information for each detected/decoded bit or codeword syndrome value.

摘要翻译： 所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。 在本发明的一个方面，所公开的技术为每个检测/解码的比特或码字综合征值计算软可靠性信息。

公开(公告)号：US08032812B1

公开(公告)日：2011-10-04

申请号：US11867356

申请日：2007-10-04

申请人： Xueshi Yang ,  Zining Wu ,  Heng Tang

发明人： Xueshi Yang ,  Zining Wu ,  Heng Tang

IPC分类号： H03M13/00

CPC分类号： H04L1/0052 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/2909 ,  H03M13/293 ,  H04L1/0065

摘要： A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.

摘要翻译： 用于纠错解码的方法和系统使用连接的纠错解码器。 信道解码器从传输信道接收编码用户数据，对用户数据的比特进行解码，并生成解码比特的擦除信息。 解码的比特和擦除信息由外部ECC解码器接收，该外部ECC解码器首先执行擦除解码。 如果擦除解码成功，则输出解码的用户数据。 如果擦除解码不成功，则外部ECC解码器执行更复杂的错误解码。 因此，不需要对可以使用擦除解码成功解码的用户数据执行错误解码。 避免执行错误解码所需的额外操作。 以这种方式，减少整体解码过程的复杂性，显着降低所需的计算能力，同时保持所需的性能水平。