公开(公告)号：US5329460A

公开(公告)日：1994-07-12

申请号：US12573

申请日：1993-02-01

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

公开(公告)号：US5255203A

公开(公告)日：1993-10-19

申请号：US538211

申请日：1990-06-14

申请人： Om P. Agrawal ,  Michael J. Wright

发明人： Om P. Agrawal ,  Michael J. Wright

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array. Further, the interconnect structure has programmable interconnection between long lines and bidirectional general interconnect segments.

摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。 此外，互连结构在长线和双向通用互连段之间具有可编程互连。

公开(公告)号：US5225719A

公开(公告)日：1993-07-06

申请号：US699427

申请日：1991-05-13

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US5191242A

公开(公告)日：1993-03-02

申请号：US701790

申请日：1991-05-17

申请人： Om P. Agrawal ,  Michael J. Wright

发明人： Om P. Agrawal ,  Michael J. Wright

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： An integrated circuit device which implements a plurality of programmable digital logic functions derived from a number of digital logic inputs and further includes an on-chip digital-to-analog converter providing an analog output current signal responsive to the programmable logic functions derived from the digital inputs is provided. The means for implementing the programmable logic functions may include a programmable logic circuit having a programmable AND array comprising a plurality of AND gates, each with a plurality of inputs and at least one output. The AND gate inputs are selectively programmable with the input terms to generate an output signal to the AND gate outputs. The device further includes an OR gate array having a plurality of OR gates, each of the OR gates including a plurality of inputs and an output, thereby providing a plurality of OR gate array outputs generating a plurality of digital logic signals. The digital-to-analog converter includes a plurality of inputs coupled to a subset of the plurality of OR gate array outputs for converting the digital signals present on the OR gate array outputs into a variable amplitude output signal. In one embodiment, an 8-to-8 encoder providing the outputs of the subset of OR gate array outputs to the inputs of the digital-to-analog converter is also included.

摘要翻译： 一种集成电路装置，其实现从多个数字逻辑输入导出的多个可编程数字逻辑功能，并且还包括片上数模转换器，其提供模拟输出电流信号，该模拟输出电流信号响应于从数字 提供输入。 用于实现可编程逻辑功能的装置可以包括具有可编程AND阵列的可编程逻辑电路，该可编程逻辑电路包括多个与门，每个与门具有多个输入和至少一个输出。 与门输入可选择性地与输入项可编程，以产生与门输出的输出信号。 该器件还包括具有多个或门的或门阵列，每个或门包括多个输入和一个输出，从而提供产生多个数字逻辑信号的多个OR门阵列输出。 数模转换器包括耦合到多个OR门阵列输出的子集的多个输入，用于将存在于或门阵列输出上的数字信号转换成可变幅度输出信号。 在一个实施例中，还包括提供OR门阵列输出的子集的输出到数模转换器的输入端的8比8编码器。

公开(公告)号：US5185706A

公开(公告)日：1993-02-09

申请号：US503049

申请日：1990-04-02

申请人： Om P. Agrawal ,  Michael J. Wright

发明人： Om P. Agrawal ,  Michael J. Wright

IPC分类号： G06F13/38 ,  H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1735 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： A configurable logic array, includes a plurality of configurable logic cells which include a tristate output buffer, having an input receiving a logic signal from within the configurable logic cell, an output connected to the configurable interconnect structure and an output enable input. A plurality of selectors, controlled by the configuration memory, supply output enable signals for controlling corresponding tristate output buffers. The inputs to the plurality of selectors include a "common output enable signal," and at least a second logic signal, such as a constant high or constant low logic level. A circuit responsive to program data in the configuration memory and input signals from the interconnect structure generates the common output enable signal. One input of the selector is provided by an invertor connected from the input of the tristate output buffer to the selector for connecting an output signal to a long line in a wired-AND configuration.

摘要翻译： 可配置逻辑阵列包括多个可配置逻辑单元，其包括三态输出缓冲器，其具有从可配置逻辑单元内接收逻辑信号的输入，连接到可配置互连结构的输出和输出使能输入。 由配置存储器控制的多个选择器提供用于控制相应三态输出缓冲器的输出使能信号。 多个选择器的输入包括“公共输出使能信号”和至少第二逻辑信号，例如恒定的高或恒定的低逻辑电平。 响应于配置存储器中的程序数据和来自互连结构的输入信号的电路产生公共输出使能信号。 选择器的一个输入由从三通输出缓冲器的输入端连接到选择器的反相器提供，该选择器用于将输出信号连接到具有线配置的长线路。

公开(公告)号：US5153462A

公开(公告)日：1992-10-06

申请号：US703455

申请日：1991-05-21

申请人： Om P. Agrawal ,  Michael J. Wright ,  Steve Sidman

发明人： Om P. Agrawal ,  Michael J. Wright ,  Steve Sidman

IPC分类号： G06J1/00 ,  H03K3/0233 ,  H03K19/177

CPC分类号： H03K19/17732 ,  G06J1/00 ,  H03K19/17716 ,  H03K3/02337

摘要： A single integrated circuit including programmable logic having a plurality of inputs and a plurality of outputs, with at least one input of the programmable logic coupled to an on-chip analog comparator is provided. In one aspect of the invention, a voltage comparator having programmable hysteresis for setting the output state switching thresholds of the comparator is utilized. In another aspect of the invention, the programmable logic comprises a programmable combinatorial array having a programmable AND array and a fixed OR array. The integrated circuit further comprises an output block including a plurality of flip-flops and output buffers coupled to at least one I/O pin for selectively determining the state of the I/O pin. In yet another aspect the invention, the programmable combinatorial array includes a plurality of AND array outputs, divided into three subsets, for input to three pairs of OR gates which comprise the fixed OR plane of the device.

摘要翻译： 提供了包括具有多个输入和多个输出的可编程逻辑的单个集成电路，其中耦合到片上模拟比较器的可编程逻辑的至少一个输入。 在本发明的一个方面，利用具有用于设定比较器的输出状态切换阈值的可编程滞后的电压比较器。 在本发明的另一方面，可编程逻辑包括具有可编程AND阵列和固定OR阵列的可编程组合阵列。 集成电路还包括输出块，其包括耦合到至少一个I / O引脚的多个触发器和输出缓冲器，用于选择性地确定I / O引脚的状态。 在本发明的另一方面，可编程组合阵列包括被分成三个子集的多个AND阵列输出，用于输入到包括装置的固定OR平面的三对OR门。

公开(公告)号：US07459935B1

公开(公告)日：2008-12-02

申请号：US12060776

申请日：2008-04-01

申请人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

发明人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide distributed random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure. In one embodiment, there are at least twice as many logic blocks in the first plurality of logic blocks than in the second plurality of logic blocks. In another embodiment, the first and second plurality of logic blocks are arranged in one or more rows, and the programmable logic device includes one or more rows of embedded block RAM.

摘要翻译： 可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口和提供可编程逻辑功能的第一和第二多个逻辑块的多个输入/输出块，只有第二多个逻辑块进一步适于提供分布式 随机存取功能。 路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。 配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构。 在一个实施例中，在第一多个逻辑块中比在第二多个逻辑块中存在至少两倍的逻辑块。 在另一个实施例中，第一和第二多个逻辑块被布置成一行或多行，并且可编程逻辑器件包括一行或多行嵌入块RAM。

公开(公告)号：US07355441B1

公开(公告)日：2008-04-08

申请号：US11360337

申请日：2006-02-22

申请人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

发明人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure, with at least one block of non-volatile memory to store configuration data that can be transferred to the configuration memory cells.

摘要翻译： 根据本发明的一个或多个实施例公开了系统和方法，以向可编程逻辑器件提供非易失性存储器和可变量的分布式存储器（例如，以成本有效的方式）。 例如，根据本发明的实施例，可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口的多个输入/输出块以及提供可编程逻辑功能的第一和第二多个逻辑块， 只有第二多个逻辑块进一步适于提供随机存取存储器功能。 路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。 配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构，具有至少一个非易失性存储器块以存储可以传送到配置存储器的配置数据 细胞。

公开(公告)号：US07208975B1

公开(公告)日：2007-04-24

申请号：US11040772

申请日：2005-01-20

申请人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

发明人： Om P. Agrawal ,  Jock Tomlinson ,  Kuang Chi ,  Ji Zhao ,  Ju Shen ,  Jinghui Zhu

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

摘要翻译： 在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。 布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路 具有确定性的路由延迟。 在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

公开(公告)号：US07088134B1

公开(公告)日：2006-08-08

申请号：US10704025

申请日：2003-11-06

申请人： Om P. Agrawal ,  Jason Cheng ,  Paul R. Bonwick ,  Bradley Felton ,  Andrew Armitage

发明人： Om P. Agrawal ,  Jason Cheng ,  Paul R. Bonwick ,  Bradley Felton ,  Andrew Armitage

IPC分类号： H01L25/01

CPC分类号： H03K19/1776 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.

摘要翻译： 可编程逻辑器件包括组织成簇的多个逻辑块。 每个逻辑块可以被配置为逻辑模式和存储器模式。 逻辑块被布置成至少一个簇，每个簇具有被配置为向其簇内的逻辑块提供数据字的数据总线。