公开(公告)号：US5598346A

公开(公告)日：1997-01-28

申请号：US596679

申请日：1996-02-05

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes an internal clock selector for selecting a CLB-internal clock and at least one register that is responsive to the selected CLB-internal clock. The configurable interconnect network includes clock-carrying longlines extending in different directions past each CLB for broadcasting clock signals. The broadcast clock signals can originate outside the programmable integrated circuit or such broadcast clock signals can be generated within one or more of the CLB's and thereafter broadcast by way of the clock broadcasting longlines to others of the CLB's.

摘要翻译： 可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。 每个CLB包括用于选择CLB内部时钟的内部时钟选择器和响应于所选CLB内部时钟的至少一个寄存器。 可配置互连网络包括延伸穿过每个CLB的不同方向的时钟传送延长线，用于广播时钟信号。 广播时钟信号可以起源于可编程集成电路之外，或者这种广播时钟信号可以在一个或多个CLB内产生，然后通过时钟广播延长线向CLB的其他人广播。

公开(公告)号：US5469368A

公开(公告)日：1995-11-21

申请号：US462934

申请日：1995-06-05

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a plurality of function lookup tables (LUT's) each defined by a bit storage area and a select means responsive to input signals for selecting a stored bit. The design includes first and second LUT's where the first LUT output determines whether the output of the second LUT will be forwarded or replaced by another function output.

摘要翻译： 可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。 每个CLB包括由比特存储区域定义的多个功能查找表（LUT）和响应于用于选择存储的比特的输入信号的选择装置。 该设计包括第一和第二LUT，其中第一LUT输出确定第二LUT的输出是否将被另一个功能输出转发或替换。

公开(公告)号：US5212652A

公开(公告)日：1993-05-18

申请号：US394221

申请日：1989-08-15

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of contact signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

公开(公告)号：US5621650A

公开(公告)日：1997-04-15

申请号：US456946

申请日：1995-06-01

申请人： Om P. Agrawal ,  Michael J. Wright

发明人： Om P. Agrawal ,  Michael J. Wright

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17744 ,  H03K19/1737 ,  H03K19/17704

摘要： A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

公开(公告)号：US5349544A

公开(公告)日：1994-09-20

申请号：US207317

申请日：1988-06-15

申请人： Michael J. Wright ,  Om P. Agrawal

发明人： Michael J. Wright ,  Om P. Agrawal

IPC分类号： H03K19/177 ,  H03L7/06 ,  H03L7/183 ,  G06J1/00

CPC分类号： H03L7/183

摘要： A PLL is integrated on the same chip as a programmable logic circuit and interconnected therewith in any of several useful ways. In one aspect of the invention, the output frequency of the PLL may be connected to the clock input of registers in the programmable logic circuit. If the PLL performs frequency multiplication, the chip then becomes a high-speed state machine synchronized to a lower-frequency input clock. In another aspect of the invention, the signal present at different parts of the phase lock loop may be provided to inputs of the programmable logic circuit. In another aspect, outputs of the programmable logic circuit may be used to control the operation and/or characteristics of various components in the PLL. For example, if a counter is included in the phase lock loop for causing the loop to generate a frequency multiple of the input signal, the counter may be made programmable according to outputs of the state machine. Similarly, the characteristics of the phase detector or loop filter may be dynamically adjusted according to outputs of the state machine. In yet another aspect of the invention, an output of the programmable logic circuit is, or is used to generate, one of the inputs to the phase detector in the PLL.

摘要翻译： PLL与可编程逻辑电路集成在同一个芯片上，并以几种有用的方式进行互连。 在本发明的一个方面，PLL的输出频率可以连接到可编程逻辑电路中的寄存器的时钟输入。 如果PLL执行倍频，芯片就成为与低频输入时钟同步的高速状态机。 在本发明的另一方面，存在于锁相环的不同部分的信号可以被提供给可编程逻辑电路的输入端。 在另一方面，可编程逻辑电路的输出可用于控制PLL中的各种组件的操作和/或特性。 例如，如果在锁相环中包括计数器以使环路产生输入信号的频率倍数，则可以根据状态机的输出使计数器可编程。 类似地，可以根据状态机的输出来动态调整相位检测器或环路滤波器的特性。 在本发明的另一方面，可编程逻辑电路的输出是或用于产生PLL中的相位检测器的输入之一。

公开(公告)号：US5587921A

公开(公告)日：1996-12-24

申请号：US560933

申请日：1995-11-20

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a lookup table having inputs and outputs, a first multiplexer means for applying a selected subset of CLB input signals to the lookup table inputs, and a second multiplexer means for routing lookup table output signals to selectable destinations. The first multiplexer means can programmably route input signals to the lookup table inputs from a variety of sources including first through fourth direct-connect receiving terminals distributed symmetrically about the CLB, first through fourth longline receiving terminals distributed symmetrically about the CLB, first through fourth general-interconnect receiving terminals distributed symmetrically about the CLB, and first through fourth feedback means distributed symmetrically within the CLB. The second multiplexer means can programmably route output signals from the lookup table to first through fourth output macrocells distributed symmetrically about the CLB. The first through fourth output macrocells can respectively couple the routed signals to first through fourth direct-connect outputting terminals distributed symmetrically about the CLB, first through fourth tristate outputting terminals distributed symmetrically about the CLB, and the first through fourth feedback means.

摘要翻译： 可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。 每个CLB包括具有输入和输出的查找表，用于将选定的CLB输入信号的子集应用于查找表输入的第一多路复用器装置和用于将查找表输出信号路由到可选目的地的第二多路复用器装置。 第一多路复用器装置可编程地将输入信号路由到各种源的查找表输入，包括关于CLB对称分布的第一至第四直接接收终端，关于CLB对称分布的第一至第四延长线接收终端，第一至第四通用 - 关于CLB对称分布的接收端子以及在CLB内对称分布的第一至第四反馈装置。 第二多路复用器装置可编程地将来自查找表的输出信号路由到关于CLB对称分布的第一到第四输出宏小区。 第一到第四输出宏单元可以分别将路由信号耦合到关于CLB对称地分布的第一到第四直接连接输出端子，关于CLB对称地分布的第一到第四三态输出端子以及第一到第四反馈装置。

公开(公告)号：US5359536A

公开(公告)日：1994-10-25

申请号：US25551

申请日：1993-03-03

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： G06F7/00 ,  G06F7/575 ,  G06F17/50 ,  H03K17/693 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17744

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

公开(公告)号：US5260881A

公开(公告)日：1993-11-09

申请号：US442528

申请日：1989-11-27

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17792

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

公开(公告)号：US5233539A

公开(公告)日：1993-08-03

申请号：US429125

申请日：1989-10-30

申请人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

发明人： Om P. Agrawal ,  Michael J. Wright ,  Ju Shen

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

摘要翻译： 具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。 互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。 此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。 相反，未提交的长行致力于连接到互连的其他段。 互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。 可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。 互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

公开(公告)号：US4963768A

公开(公告)日：1990-10-16

申请号：US243574

申请日：1988-09-12

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein ,  Michael J. Wright ,  Jerry D. Moench ,  Arthur H. Khu

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein ,  Michael J. Wright ,  Jerry D. Moench ,  Arthur H. Khu

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17708 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17744

摘要： A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.

摘要翻译： 高密度分段可编程阵列逻辑器件利用开关互连矩阵耦合可编程逻辑单元阵列。 每个可编程逻辑单元包括可编程输入逻辑宏单元，可编程反馈逻辑宏单元，可编程输出逻辑宏单元，埋入状态逻辑宏单元以及可编程与门和或门组合。 每个输入宏单元，输出宏单元和掩埋状态宏单元具有用于响应于对单元的输入信号而产生已注册/锁存的输出信号或组合输出信号的装置。 各种开关用于将信号耦合到可编程“与”门和“或”门的组合。