AUTOMATIC DETERMINATION OF POWER PLANE SHAPE IN PRINTED CIRCUIT BOARD

    公开(公告)号:US20200100354A1

    公开(公告)日:2020-03-26

    申请号:US16140611

    申请日:2018-09-25

    Abstract: A system and method to automatically determine power plane shape in a printed circuit board (PCB) involve obtaining inputs. The inputs include a size and shape of the PCB, a set of sources, and a set of sinks associated with a power plane. The method also includes determining a center of charge (CoC) as a center of largest current density for the set of sources and the set of sinks, and creating a sub-shape corresponding with a path from each source of the set of sources and from each sink of the set of sinks to the CoC. The creating the sub-shape includes determining a width of a conductor in the path corresponding with each of the sub-shapes. The sub-shapes created for the set of sources and the set of sinks are combined as the power plane shape.

    Cable cassette apparatus
    72.
    发明授权

    公开(公告)号:US10289170B2

    公开(公告)日:2019-05-14

    申请号:US15945857

    申请日:2018-04-05

    Abstract: An apparatus includes a cassette. The cassette includes a carriage. The carriage is retained internally to the cassette. The apparatus further includes a booklet assembly. The booklet assembly includes a cable connector. The cable connector is affixed internally to the booklet assembly. The cassette is configured for insertion into the booklet assembly. The apparatus further includes a cable assembly. The cable assembly is configured for insertion into the cable connector. The carriage is configured for retaining the cable assembly. In an aspect, a method of using the apparatus includes preloading the cable assembly into the carriage, inserting the cassette into the booklet assembly, and configuring the carriage such that the cable assembly is inserted into the cable connector and retained in an inserted position by the carriage.

    Signal via positioning in a multi-layer circuit board using a genetic via placement solver

    公开(公告)号:US10223490B2

    公开(公告)日:2019-03-05

    申请号:US15813233

    申请日:2017-11-15

    Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

    Signal via positioning in a multi-layer circuit board using a genetic via placement solver

    公开(公告)号:US10216884B2

    公开(公告)日:2019-02-26

    申请号:US15813236

    申请日:2017-11-15

    Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

    CABLE CASSETTE APPARATUS
    75.
    发明申请

    公开(公告)号:US20180224904A1

    公开(公告)日:2018-08-09

    申请号:US15945848

    申请日:2018-04-05

    CPC classification number: G06F1/183

    Abstract: An apparatus includes a cassette. The cassette includes a carriage. The carriage is retained internally to the cassette. The apparatus further includes a booklet assembly. The booklet assembly includes a cable connector. The cable connector is affixed internally to the booklet assembly. The cassette is configured for insertion into the booklet assembly. The apparatus further includes a cable assembly. The cable assembly is configured for insertion into the cable connector. The carriage is configured for retaining the cable assembly. In an aspect, a method of using the apparatus includes preloading the cable assembly into the carriage, inserting the cassette into the booklet assembly, and configuring the carriage such that the cable assembly is inserted into the cable connector and retained in an inserted position by the carriage.

    Cable cassette apparatus
    76.
    发明授权

    公开(公告)号:US10019044B2

    公开(公告)日:2018-07-10

    申请号:US15662776

    申请日:2017-07-28

    CPC classification number: G06F1/183

    Abstract: An apparatus includes a cassette. The cassette includes a carriage. The carriage is retained internally to the cassette. The apparatus further includes a booklet assembly. The booklet assembly includes a cable connector. The cable connector is affixed internally to the booklet assembly. The cassette is configured for insertion into the booklet assembly. The apparatus further includes a cable assembly. The cable assembly is configured for insertion into the cable connector. The carriage is configured for retaining the cable assembly. In an aspect, a method of using the apparatus includes preloading the cable assembly into the carriage, inserting the cassette into the booklet assembly, and configuring the carriage such that the cable assembly is inserted into the cable connector and retained in an inserted position by the carriage.

    Signal via positioning in a multi-layer circuit board

    公开(公告)号:US09940426B2

    公开(公告)日:2018-04-10

    申请号:US14842862

    申请日:2015-09-02

    CPC classification number: G06F17/5077

    Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.

    DIMM CONNECTOR REGION VIAS AND ROUTING
    80.
    发明申请
    DIMM CONNECTOR REGION VIAS AND ROUTING 有权
    DIMM连接器区域和路由

    公开(公告)号:US20170062960A1

    公开(公告)日:2017-03-02

    申请号:US15248652

    申请日:2016-08-26

    Abstract: A dual in-line memory module (DIMM) connector system is provided. The DIMM connector system includes a motherboard, a DIMM card and a connector by which the DIMM card is coupled with the motherboard. The motherboard includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, ground pads disposed proximate to signal pads, signal vias connected to distal edges of signal pads and shared antipads. The DIMM card includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, signal vias connected to distal edges of signal pads and shared antipads for respective pairs of signal vias.

    Abstract translation: 提供双列直插式内存模块(DIMM)连接器系统。 DIMM连接器系统包括主板,DIMM卡和DIMM卡与主板耦合的连接器。 主板包括由中间损耗介电常数材料形成的印刷电路板(PCB),比接地焊盘更薄的信号焊盘,靠近信号焊盘设置的接地焊盘,连接到信号焊盘的远端边缘的信号通孔和共享的反焊盘。 DIMM卡包括由中间损耗介电常数材料形成的印刷电路板(PCB),比接地焊盘薄的信号焊盘,连接到信号焊盘的远端边缘的信号通孔和用于相应的信号通道对的共用反接头。

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