公开(公告)号：US11289371B2

公开(公告)日：2022-03-29

申请号：US16750040

申请日：2020-01-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Nicholas Anthony Lanzillo ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

Abstract: Integrated chips and methods of forming the same include forming conductive lines on an underlying layer, between regions of dielectric material. The regions of dielectric material are selectively patterned, leaving at least one dielectric remnant region. An interlayer dielectric is formed over the underlying layer and the at least one dielectric remnant region, between the conductive lines.

公开(公告)号：US11232977B2

公开(公告)日：2022-01-25

申请号：US16787240

申请日：2020-02-11

Applicant: International Business Machines Corporation

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

公开(公告)号：US11195795B1

公开(公告)日：2021-12-07

申请号：US16891143

申请日：2020-06-03

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.

公开(公告)号：US11177160B2

公开(公告)日：2021-11-16

申请号：US16828551

申请日：2020-03-24

Applicant: International Business Machines Corporation

Inventor： Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a first mandrel layer and a second mandrel layer on the dielectric layer and patterning the first mandrel layer and the second mandrel layer to form respective first and second patterns in the first and second mandrel layers. The first pattern includes a first line segment and a first wing segment. The first wing segment is filled with a first spacer material to form a first spacer. The method further includes removing exposed portions of the first and second mandrel layers, transferring an image of the first and second patterns, patterning the dielectric layer and depositing a metal into the patterned dielectric layer to form a metallic interconnect structure. The metallic interconnect structure includes first and second metallic lines with the second metallic line having a line break corresponding to the first spacer.

公开(公告)号：US11158536B2

公开(公告)日：2021-10-26

申请号：US16736478

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Daniel James Dechene ,  Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

公开(公告)号：US11152299B2

公开(公告)日：2021-10-19

申请号：US16807392

申请日：2020-03-03

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Hosadurga Shobha ,  Lawrence A. Clevenger ,  Robert Robison

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A technique relates to an integrated circuit. A first dielectric material is formed on a layer, and a second dielectric material is formed on the first dielectric material, the second dielectric material having a different characteristic than the first dielectric material. Conductive material is formed in the first dielectric material, the second dielectric material, and the layer, the conductive material forming interconnects in the layer separated by a stack of the first dielectric material and the second dielectric material. The conductive material forms a self-aligned conductive via on one of the interconnects according to a topography of the stack, the stack of the first dielectric material and the second dielectric material electrically insulating the one of the interconnects from another one of the interconnects.

公开(公告)号：US20210280510A1

公开(公告)日：2021-09-09

申请号：US16807392

申请日：2020-03-03

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Hosadurga Shobha ,  Lawrence A. Clevenger ,  Robert Robison

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A technique relates to an integrated circuit. A first dielectric material is formed on a layer, and a second dielectric material is formed on the first dielectric material, the second dielectric material having a different characteristic than the first dielectric material. Conductive material is formed in the first dielectric material, the second dielectric material, and the layer, the conductive material forming interconnects in the layer separated by a stack of the first dielectric material and the second dielectric material. The conductive material forms a self-aligned conductive via on one of the interconnects according to a topography of the stack, the stack of the first dielectric material and the second dielectric material electrically insulating the one of the interconnects from another one of the interconnects.

公开(公告)号：US20210280457A1

公开(公告)日：2021-09-09

申请号：US16811291

申请日：2020-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Nicholas Anthony Lanzillo ,  Daniel James Dechene ,  Robert Robison

IPC: H01L21/768 ,  H01L23/522

Abstract: Embodiments of the present invention disclose a method and apparatus for making a multi-layer device comprising a conductive layer, a dielectric layer formed on top of conductive layer, a via pattern formed in the dielectric layer, wherein the via pattern is comprised of a plurality of channels and columns, wherein a first portion of the via pattern downwards extends through the entire dielectric layer to directly contact the conductive layer, wherein a second portion of the via pattern extends downwards without coming into direct contact with the conductive layer.

公开(公告)号：US20210233808A1

公开(公告)日：2021-07-29

申请号：US16750062

申请日：2020-01-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: Integrated chips and methods of forming the same include forming a conductive layer to a line height. A dielectric layer is formed over the conductive layer to a via height, with at least one opening that exposes a via region of the conductive layer. A conductive via is formed in the opening having the via height. The conductive layer is patterned to form a conductive line having the line height.

公开(公告)号：US20210225761A1

公开(公告)日：2021-07-22

申请号：US16749476

申请日：2020-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Robert Robison

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

Abstract: Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.