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    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION
    71.
    发明申请
    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION 有权

    公开(公告)号：US20210103682A1

    公开(公告)日：2021-04-08

    申请号：US17020486

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Siddhartha Chhabra ,  Nadav Bonen

    IPC: G06F21/79 ,  G06F21/75 ,  G06F21/76 ,  G06F12/14

    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.

    SM4 acceleration processors, methods, systems, and instructions
    77.
    发明授权
    SM4 acceleration processors, methods, systems, and instructions 有权

    公开(公告)号：US10447468B2

    公开(公告)日：2019-10-15

    申请号：US16147646

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Vlad Krasnov

    IPC: H04L29/06 ,  H04L9/06 ,  G06F9/30 ,  G06F21/60

    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION
    79.
    发明申请
    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION 审中-公开

    公开(公告)号：US20190102577A1

    公开(公告)日：2019-04-04

    申请号：US15720360

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Siddhartha Chhabra ,  Nadav Bonen

    IPC: G06F21/79 ,  G06F21/76 ,  G06F21/75

    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.

    Memory monitor
    80.
    发明授权
    Memory monitor 有权

    公开(公告)号：US10248486B2

    公开(公告)日：2019-04-02

    申请号：US15279697

    申请日：2016-09-29

    Applicant: Intel Corporation

    Inventor： Rodrigo R. Branco ,  Shay Gueron

    IPC: G06F11/07 ,  G06F21/50 ,  G06F9/4401

    Abstract: Various systems and methods for providing a memory monitor are provided herein. An integrated circuit and memory are disposed in a computer system. The integrated circuit to monitor main memory includes: a detection circuit to detect that the computer system enters a sleep state; a test circuit to test for the presence of the main memory; and a recovery circuit to perform a recovery process when the test fails.

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