公开(公告)号：US6020774A

公开(公告)日：2000-02-01

申请号：US121296

申请日：1998-07-23

Applicant: You-Ming Chiu ,  Jiin Lai

Inventor： You-Ming Chiu ,  Jiin Lai

IPC: G06F1/10 ,  G06F17/50 ,  H03K1/04

CPC classification number: G06F17/505 ,  G06F1/10 ,  G06F2217/62

Abstract: A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements that are directly driven by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal outputted from each of the control gates under control by the control signal. The gated CTS method comprises the steps of grouping the first logic elements into a plurality of groups, connecting each group of the first logic elements via a first buffer to one of the control gates, connecting each of the second logic elements via a second buffer to the clock generator, and connecting one input end of each of the control gates to the clock generator.

Abstract translation: 提供门控时钟树合成（CTS）方法用于合成门阵列逻辑电路以允许逻辑电路上的门阵列的最佳拓扑排列。 这又允许逻辑电路更有效地操作。 逻辑电路包括至少一个时钟发生器，多个控制栅极，每个控制栅极具有一个连接到控制信号的输入端，另一个输入端连接以从时钟发生器接收输出时钟信号;多个第一逻辑元件， 由来自时钟发生器的输出时钟信号直接驱动，以及多个第二逻辑元件，其由控制信号控制的每个控制门输出的门控时钟信号驱动。 门控CTS方法包括以下步骤：将第一逻辑元件分组成多个组，将每组第一逻辑元件经由第一缓冲器连接到控制门之一，将第二逻辑元件经由第二缓冲器连接到 时钟发生器，并且将每个控制门的一个输入端连接到时钟发生器。

公开(公告)号：US08812782B2

公开(公告)日：2014-08-19

申请号：US12694470

申请日：2010-01-27

Applicant: Jian Li ,  Jiin Lai ,  Shan-Na Pang ,  Zhi-Qiang Hui ,  Di Dai

Inventor： Jian Li ,  Jiin Lai ,  Shan-Na Pang ,  Zhi-Qiang Hui ,  Di Dai

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1036

Abstract: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.

Abstract translation: 存储器管理系统和方法包括并使用高速缓冲存储器（例如，表查看缓冲器，TLB），存储器映射表，暂存器缓存和存储器控制器。 高速缓存缓冲器被配置为存储多个数据结构。 存储器映射表被配置为存储数据结构的多个地址。 暂存器缓存被配置为存储数据结构的基址。 存储器控制器被配置为控制高速缓冲存储器和暂存器缓存中的读写。 这些组件在存储器控制器的控制下一起可操作，以便有效地搜索存储器管理系统中的数据结构。

公开(公告)号：US08656074B2

公开(公告)日：2014-02-18

申请号：US12862134

申请日：2010-08-24

Applicant: Jiin Lai ,  Buheng Xu ,  Jinkuan Tang

Inventor： Jiin Lai ,  Buheng Xu ,  Jinkuan Tang

IPC: G06F13/12 ,  G06F13/38

CPC classification number: G06F13/385 ,  G06F11/08 ,  G06F13/00 ,  G06F13/12

Abstract: A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device.

Abstract translation: 提供数据传输系统。 数据传输系统包括耦合到第一设备的第一控制电路，耦合到第一控制电路的平移电路和耦合到转换电路的第二控制电路。 第一控制电路解码由第一设备发送的第一格式数据分组。 翻译电路接收解码的第一格式数据分组，并将解码的第一格式数据分组转换为第二格式数据分组。 第二控制电路将第二格式数据包发送到主机。 第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备。

公开(公告)号：US08452909B2

公开(公告)日：2013-05-28

申请号：US12959277

申请日：2010-12-02

Applicant: Jinkuan Tang ,  Jiin Lai ,  Buheng Xu ,  Hui Jiang

Inventor： Jinkuan Tang ,  Jiin Lai ,  Buheng Xu ,  Hui Jiang

IPC: G06F13/20 ,  G06F13/38

CPC classification number: G06F13/385 ,  G06F13/4059

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.

Abstract translation: 本发明涉及通用串行总线（USB）事务转换器和微帧同步方法。 设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。 配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。 控制器交替地将数据存储在缓冲器中。 使用起始帧（SOF）计数器对SOF分组进行计数，其中将SOF计数器的计数值与预定义的值进行比较。 具体地，当计数值达到预定义值或大于预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）以相同的方式发送 时间。 此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。

公开(公告)号：US20120106949A1

公开(公告)日：2012-05-03

申请号：US13018548

申请日：2011-02-01

Applicant: Jin-Kuan Tang ,  Jiin Lai

Inventor： Jin-Kuan Tang ,  Jiin Lai

IPC: H04B10/08

CPC classification number: H04B10/40

Abstract: An optical transceiver module adapted to a link device includes a connection unit, a driving unit and optical transmitting and receiving units. The connection unit, to be coupled with the link device, includes an indicating element for generating an indicating signal when the connection unit is coupled with the link device. The driving unit, coupled with the connection unit, receives the indicating signal and outputs a control signal according to the indicating signal. The optical transmitting unit, coupled with the driving unit, receives the control signal for driving the optical transmitting unit to output a first optical signal. The optical receiving unit, coupled with the driving unit, transmits a received second optical signal to the driving unit. An optical transmission device using the optical transceiver module, and an optical transmission method are also disclosed. A link training sequence can be initiated after the connection unit is actually coupled with the link device. Thus, a host cannot enter a disable mode due to error connection.

Abstract translation: 适于链接装置的光收发模块包括连接单元，驱动单元和光发射和接收单元。 要与链接装置耦合的连接单元包括用于当连接单元与链接装置耦合时产生指示信号的指示元件。 与连接单元耦合的驱动单元接收指示信号，并根据指示信号输出控制信号。 与驱动单元耦合的光发送单元接收用于驱动光发送单元的控制信号以输出第一光信号。 光接收单元与驱动单元耦合，将接收到的第二光信号发送到驱动单元。 还公开了使用光收发模块的光传输装置和光传输方法。 链路训练序列可以在连接单元实际上与链路设备耦合之后启动。 因此，由于错误连接，主机无法进入禁用模式。

公开(公告)号：US20110119557A1

公开(公告)日：2011-05-19

申请号：US12872526

申请日：2010-08-31

Applicant: Xingchen Chen ,  Jiin Lai ,  Di Dai ,  Shanna Pang

Inventor： Xingchen Chen ,  Jiin Lai ,  Di Dai ,  Shanna Pang

IPC: G06F11/08 ,  G06F13/28

CPC classification number: G06F13/28

Abstract: A data transmission method for a universal serial bus (USB) host controller is provided. First, input data is received. A cyclic redundancy check (CRC) result of the input data is calculated, and, simultaneously, the input data is transmitted to a system memory of a host. Then, it is determined whether the input data is the last input data of a data packet. When it is determined that the input data is the last input data of the data packet, the CRC result of the last input data of the data packet is calculated. Thus, the CRC result of the data packet is accumulated. The accumulated CRC result is combined with the last input data, and transmitted the combination to the system memory of the host.

Abstract translation: 提供了一种用于通用串行总线（USB）主机控制器的数据传输方法。 首先，接收输入数据。 计算输入数据的循环冗余校验（CRC）结果，同时将输入数据发送到主机的系统存储器。 然后，确定输入数据是否是数据分组的最后输入数据。 当确定输入数据是数据分组的最后输入数据时，计算数据分组的最后输入数据的CRC结果。 因此，累积了数据分组的CRC结果。 累积CRC结果与最后一个输入数据组合，并将组合传输到主机的系统存储器。

公开(公告)号：US07782313B2

公开(公告)日：2010-08-24

申请号：US11554787

申请日：2006-10-31

Applicant: Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

Inventor： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

IPC: G09G5/36 ,  G06F1/00

CPC classification number: G09G5/00 ,  G09G2330/022

Abstract: Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

Abstract translation: 包括用于降低计算机系统功耗的系统和方法。 方法的至少一个实施例包括在正常模式下处理数据，接收转换到空闲模式的指示，捕获至少一帧显示数据，以及发送所捕获的显示数据帧以便在 空闲模式

公开(公告)号：US07757031B2

公开(公告)日：2010-07-13

申请号：US11876579

申请日：2007-10-22

Applicant: Ruei-Ling Lin ,  Jiin Lai

Inventor： Ruei-Ling Lin ,  Jiin Lai

IPC: G06F13/36 ,  G06F13/00 ,  G06F7/38

CPC classification number: G06F13/4217

Abstract: A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

Abstract translation: 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输宽度或总线传输速度。

公开(公告)号：US20100064158A1

公开(公告)日：2010-03-11

申请号：US12358412

申请日：2009-01-23

Applicant: Jiin Lai ,  Chung-Che Wu

Inventor： Jiin Lai ,  Chung-Che Wu

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.

Abstract translation: 从睡眠状态恢复。 可以接收请求以恢复计算机系统从睡眠状态到执行状态的操作。 可以启动恢复过程以将计算机系统恢复到执行状态。 恢复过程可以包括将信息从非易失性存储介质加载到计算机系统存储介质。 可以从计算机系统的处理器接收请求以访问计算机系统存储介质。 该请求可能需要访问处于执行状态的计算机系统存储介质的一部分，并且可以在恢复处理完成之前被接收。 可以确定计算机系统存储介质的部分是否已被恢复。 如果计算机系统存储介质的部分尚未被恢复，那么计算机系统存储介质的该部分可以在恢复过程中的其它部分之前从非易失性存储介质中恢复。

公开(公告)号：US07472232B2

公开(公告)日：2008-12-30

申请号：US11162407

申请日：2005-09-09

Applicant: Andrew Su ,  Jiin Lai ,  Chad Tsai

Inventor： Andrew Su ,  Jiin Lai ,  Chad Tsai

IPC: G06F12/00

CPC classification number: G06F13/404

Abstract: Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.

Abstract translation: 用于计算机系统的内部数据访问的方法和相关装置。 在计算机系统中，外设可以通过或不侦听中央处理单元（CPU）来发出对系统内存空间的访问请求。 在使用支持多个虚拟通道的芯片组服务于单个虚拟信道的外设的同时，本发明根据其窥探/非窥探属性将访问请求分配给不同的处理队列，使得读取/非窥探请求被直接路由到系统 记忆。 还通过利用不同虚拟通道的缓冲资源，分别在芯片组中缓冲来自系统存储器和CPU的响应。 通过应用访问路由调度，可以提高数据访问效率。