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    Reducing Power During Idle State
    1.
    发明申请
    Reducing Power During Idle State 有权
    空闲状态下降低功率

    公开(公告)号：US20080100606A1

    公开(公告)日：2008-05-01

    申请号：US11554787

    申请日：2006-10-31

    申请人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

    发明人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

    IPC分类号： G09G5/00

    CPC分类号： G09G5/00 ,  G09G2330/022

    摘要： Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

    摘要翻译： 包括用于降低计算机系统功耗的系统和方法。 方法的至少一个实施例包括在正常模式下处理数据，接收转换到空闲模式的指示，捕获至少一帧显示数据，以及发送所捕获的显示数据帧以便在 空闲模式

    Data transmission coordinating method
    2.
    发明申请
    Data transmission coordinating method 审中-公开
    数据传输协调方法

    公开(公告)号：US20060095633A1

    公开(公告)日：2006-05-04

    申请号：US11257260

    申请日：2005-10-24

    申请人： Ruei-Ling Lin ,  Jiin Lai

    发明人： Ruei-Ling Lin ,  Jiin Lai

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4027 ,  G06F13/4208 ,  G06F2213/0024

    摘要： A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission bandwidth or bus transmission speed.

    摘要翻译： 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输带宽或总线传输速度的位数。

    Reducing power during idle state
    5.
    发明授权
    Reducing power during idle state 有权
    在空闲状态下降低功率

    公开(公告)号：US07782313B2

    公开(公告)日：2010-08-24

    申请号：US11554787

    申请日：2006-10-31

    申请人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

    发明人： Ruei-Ling Lin ,  Jiin Lai ,  Win Sheng-Cheng

    IPC分类号： G09G5/36 ,  G06F1/00

    CPC分类号： G09G5/00 ,  G09G2330/022

    摘要： Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

    摘要翻译： 包括用于降低计算机系统功耗的系统和方法。 方法的至少一个实施例包括在正常模式下处理数据，接收转换到空闲模式的指示，捕获至少一帧显示数据，以及发送所捕获的显示数据帧以便在 空闲模式

    Data transmission coordinating method and system
    6.
    发明授权
    Data transmission coordinating method and system 有权
    数据传输协调方法和系统

    公开(公告)号：US07757031B2

    公开(公告)日：2010-07-13

    申请号：US11876579

    申请日：2007-10-22

    申请人： Ruei-Ling Lin ,  Jiin Lai

    发明人： Ruei-Ling Lin ,  Jiin Lai

    IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F7/38

    CPC分类号： G06F13/4217

    摘要： A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

    摘要翻译： 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输宽度或总线传输速度。

    Data transmission coordinating method and system
    8.
    发明申请
    Data transmission coordinating method and system 审中-公开
    数据传输协调方法和系统

    公开(公告)号：US20060095632A1

    公开(公告)日：2006-05-04

    申请号：US11257259

    申请日：2005-10-24

    申请人： Ruei-Ling Lin ,  Jiin Lai

    发明人： Ruei-Ling Lin ,  Jiin Lai

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4208

    摘要： In a data transmission coordinating method, information associated with a first transmission standard of the bridge chip is read from a memory unit of the computer system. A first signal from the bridge chip is issued to the central processing unit to inform the central processing unit of the first transmission standard of the bridge chip. A second signal is issued from the central processing unit to the bridge chip to inform the bridge chip of a second transmission standard of the central processing unit. A commonly operable transmission standard is coordinated for both the central processing unit and the bridge chip according to the first transmission standard and the second transmission standard.

    摘要翻译： 在数据传输协调方法中，从计算机系统的存储器单元读取与桥芯片的第一传输标准相关联的信息。 来自桥芯片的第一信号被发送到中央处理单元，以通知中央处理单元桥接芯片的第一传输标准。 从中央处理单元向桥接芯片发出第二信号，以向桥接芯片通知中央处理单元的第二传输标准。 根据第一传输标准和第二传输标准，为中央处理单元和桥接芯片两者协调通用的传输标准。

    DATA TRANSMISSION COORDINATING METHOD AND SYSTEM
    10.
    发明申请
    DATA TRANSMISSION COORDINATING METHOD AND SYSTEM 有权
    数据传输协调方法与系统

    公开(公告)号：US20080046618A1

    公开(公告)日：2008-02-21

    申请号：US11876579

    申请日：2007-10-22

    申请人： Ruei-Ling Lin ,  Jiin Lai

    发明人： Ruei-Ling Lin ,  Jiin Lai

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4217

    摘要： A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

    摘要翻译： 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输宽度或总线传输速度。