公开(公告)号：US20130013863A1

公开(公告)日：2013-01-10

申请号：US13613104

申请日：2012-09-13

申请人： Chen-Yong Cher ,  Michael K. Gschwind

发明人： Chen-Yong Cher ,  Michael K. Gschwind

IPC分类号： G06F12/08

CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。

公开(公告)号：US20120060016A1

公开(公告)日：2012-03-08

申请号：US12876432

申请日：2010-09-07

申请人： Alexandre E. Eichenberger ,  Michael K. Gschwind ,  Valentina Salapura

发明人： Alexandre E. Eichenberger ,  Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043

摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, a gather instruction is receive in a logic unit of a processor, the gather instruction specifying a plurality of addresses in a memory from which data is to be loaded into a target vector register of the processor. A plurality of separate load instructions for loading the data from the plurality of addresses in the memory are automatically generated within the logic unit. The plurality of separate load instructions are sent, from the logic unit, to one or more load/store units of the processor. The data corresponding to the plurality of addresses is gathered in a buffer of the processor. The logic unit then writes data stored in the buffer to the target vector register.

摘要翻译： 提供了执行分散加载操作的机构。 利用这些机制，在处理器的逻辑单元中接收收集指令，所述收集指令指定要从中将数据加载到处理器的目标向量寄存器的存储器中的多个地址。 在逻辑单元内自动生成用于从存储器中的多个地址加载数据的多个单独的加载指令。 多个单独的加载指令从逻辑单元发送到处理器的一个或多个加载/存储单元。 对应于多个地址的数据被收集在处理器的缓冲器中。 然后，逻辑单元将存储在缓冲器中的数据写入目标向量寄存器。

公开(公告)号：US20110296421A1

公开(公告)日：2011-12-01

申请号：US12787810

申请日：2010-05-26

申请人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

发明人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

IPC分类号： G06F9/52

CPC分类号： G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/5022 ,  G06F9/52 ,  G06F9/542

摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.

摘要翻译： 可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个 硬件线程。 可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。 响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。 响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

公开(公告)号：US07877582B2

公开(公告)日：2011-01-25

申请号：US12023720

申请日：2008-01-31

申请人： Michael K. Gschwind ,  Brett Olsson

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/30 ,  G06F15/76

CPC分类号： G06F9/3013 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145

摘要： A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.

摘要翻译： 可以使用标量和SIMD指令来寻址单个寄存器文件。 也就是说，根据说明性实施例的多可寻址寄存器堆中的寄存器子集可以用不同的指令形式（例如标量指令，SIMD指令等）寻址，而整个寄存器组可以用另一形式 的指令，这里称为矢量 - 标量延伸（VSX）指令。 可以使用VSX指令形式在整个寄存器组上执行的操作集基本上类似于寄存器子集的操作集。 这种布置允许传统指令访问多址寻址寄存器文件内的寄存器子集，而新的指令即VSX指令可以访问多址寻址寄存器堆中的整个寄存器范围。

公开(公告)号：US07836260B2

公开(公告)日：2010-11-16

申请号：US12147914

申请日：2008-06-27

申请人： Alan G. Gara ,  Michael K. Gschwind ,  Valentina Salapura

发明人： Alan G. Gara ,  Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3828 ,  G06F9/3842 ,  G06F9/3851 ,  G06F12/0815 ,  G06F2212/507

摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.

摘要翻译： 一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。 每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。 该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。 在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。 提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

公开(公告)号：US20100095097A1

公开(公告)日：2010-04-15

申请号：US12250575

申请日：2008-10-14

申请人： Michael K. Gschwind

发明人： Michael K. Gschwind

IPC分类号： G06F9/302

CPC分类号： G06F9/30109 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3887

摘要： Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.

摘要翻译： 提供了实现仅浮点数单指令多数据指令集架构的机制。 提供了一种处理器，其包括发布单元，耦合到发行单元的执行单元以及耦合到执行单元的向量寄存器文件。 执行单元具有实现仅浮点（FP）单指令多数据（SIMD）指令集架构（ISA）的逻辑。 向量寄存器文件的浮点向量寄存器将标量和浮点值存储为具有多个向量元素的向量。 处理器可以是数据处理系统的一部分。

公开(公告)号：US20090198977A1

公开(公告)日：2009-08-06

申请号：US12023768

申请日：2008-01-31

申请人： Michael K. Gschwind ,  Brett Olsson

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/30

CPC分类号： G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/3885

摘要： Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.

摘要翻译： 说明性实施例确定被访问的操作数的数据类型以及分析输入操作数数据类型的数据值子范围。 如果操作数的数据类型与正在处理的指令的所需格式不匹配，则确定本地是否支持输入操作数的数据类型的数据值的子范围。 如果本地不支持输入操作数的数据值的子范围，则对数据进行格式转换，然后该指令可以对数据进行操作。 否则，数据可以直接由指令操作，而不进行格式转换操作，因此不进行转换。

公开(公告)号：US07461383B2

公开(公告)日：2008-12-02

申请号：US11507307

申请日：2006-08-21

申请人： Alan G. Gara ,  Michael K. Gschwind ,  Valentina Salapura

发明人： Alan G. Gara ,  Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00

CPC分类号： G06F11/348 ,  Y02D10/34

摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.

摘要翻译： 一种用于监视大量同时事件的系统实现了具有包括计数器装置的第一计数器部分的混合计数器阵列装置，每个计数器装置用于接收表示从事件源发生的事件的信号，并提供对应于较低次序的第一计数值 混合计数器阵列的位。 第二计数器部分包括具有与计数器装置对应的可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。 控制装置监视每个计数器装置并且启动更新存储在相应的可寻址存储器位置处的对应的第二计数值的值。 当与事件相关的计数值等于阈值时，该系统包括用于向处理器设备提供快速中断触发的中断预指示。 数据传输子系统另外启用以下一个或多个：通过窄总线对第一和第二计数器部分中的计数值进行读访问或写入访问，用于初始化和确定计数状态的读/写访问 响应于处理器设备请求的被监视事件类型的值。

公开(公告)号：US20080034357A1

公开(公告)日：2008-02-07

申请号：US11462485

申请日：2006-08-04

申请人： Michael K. Gschwind

发明人： Michael K. Gschwind

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： An information handling system (IHS) employs a compiler methodology that seeks to improve the efficiency of code that executes in a multi-core processor. The compiler receives source code and converts the source code for execution using data parallel select operations that perform well in a single instruction multiple data (SIMD) environment. The compiler of the IHS may apply one or several optimization processes to the code to increase execution efficiency in a parallel processing environment.

摘要翻译： 信息处理系统（IHS）采用了一种编译器方法，旨在提高在多核处理器中执行的代码的效率。 编译器接收源代码，并使用在单个指令多数据（SIMD）环境中表现良好的数据并行选择操作来转换要执行的源代码。 IHS的编译器可以对代码应用一个或多个优化过程，以提高并行处理环境中的执行效率。

公开(公告)号：US09354874B2

公开(公告)日：2016-05-31

申请号：US13251409

申请日：2011-10-03

申请人： Michael K. Gschwind ,  Valentina Salapura

发明人： Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3005 ,  G06F9/30127 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction.