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    METHOD AND APPARATUS FOR EFFICIENT INTER-THREAD SYNCHRONIZATION FOR HELPER THREADS
    1.
    发明申请
    METHOD AND APPARATUS FOR EFFICIENT INTER-THREAD SYNCHRONIZATION FOR HELPER THREADS 有权
    用于帮助螺纹线的有效的线间同步的方法和装置

    公开(公告)号：US20110296421A1

    公开(公告)日：2011-12-01

    申请号：US12787810

    申请日：2010-05-26

    申请人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    发明人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    IPC分类号： G06F9/52

    CPC分类号： G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/5022 ,  G06F9/52 ,  G06F9/542

    摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.

    摘要翻译： 可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个 硬件线程。 可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。 响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。 响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

    METHOD AND APPARATUS FOR EFFICIENT HELPER THREAD STATE INITIALIZATION USING INTER-THREAD REGISTER COPY
    2.
    发明申请
    METHOD AND APPARATUS FOR EFFICIENT HELPER THREAD STATE INITIALIZATION USING INTER-THREAD REGISTER COPY 有权
    使用内部线程寄存器复制的有效帮助螺纹状态初始化的方法和装置

    公开(公告)号：US20110296431A1

    公开(公告)日：2011-12-01

    申请号：US12787128

    申请日：2010-05-25

    申请人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    发明人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    IPC分类号： G06F9/46

    CPC分类号： G06F9/544

    摘要： This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated hardware buffer as an intermediary storage for transferring values from registers in one thread to registers in another thread. The method may provide a generic, programmable solution that can transfer any subset of register values between threads in any given order, where the source and target registers may or may not be correlated. The method also may allow for determinate access times, since it completely bypasses the memory hierarchy. Also, the method is designed to be lightweight, focusing on communication, and keeping synchronization facilities orthogonal to the communication mechanism. It may be used by a helper thread that performs data prefetching for an application thread, for example, to initialize the upward-exposed reads in the address computation slice of the helper thread code.

    摘要翻译： 本公开描述了一种方法和系统，其可以实现线程之间的值的快速，硬件辅助，生产者 - 消费者风格的通信。 该方法在一个方面中使用专用硬件缓冲器作为用于将值从一个线程中的寄存器传送到另一线程中的寄存器的中间存储器。 该方法可以提供通用的可编程解决方案，其可以以任何给定的顺序在线程之间传送寄存器值的任何子集，其中源寄存器和目标寄存器可以或可以不相关。 该方法还可以允许确定的访问时间，因为它完全绕过存储器层次结构。 此外，该方法被设计为轻量级，专注于通信，并保持与通信机制正交的同步设备。 它可以由对应用程序线程执行数据预取的辅助线程使用，例如，初始化辅助线程代码的地址计算切片中的向上暴露的读取。

    Method and apparatus for efficient inter-thread synchronization for helper threads
    3.
    发明授权
    Method and apparatus for efficient inter-thread synchronization for helper threads 有权
    帮助线程有效的线程间同步的方法和设备

    公开(公告)号：US08468531B2

    公开(公告)日：2013-06-18

    申请号：US12787810

    申请日：2010-05-26

    申请人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    发明人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    IPC分类号： G06F9/46 ,  G06F12/08

    CPC分类号： G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/5022 ,  G06F9/52 ,  G06F9/542

    摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.

    摘要翻译： 可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个 硬件线程。 可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。 响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。 响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

    Method and apparatus for efficient helper thread state initialization using inter-thread register copy
    4.
    发明授权
    Method and apparatus for efficient helper thread state initialization using inter-thread register copy 有权
    使用线程间寄存器复制的有效帮助线程状态初始化的方法和装置

    公开(公告)号：US08453161B2

    公开(公告)日：2013-05-28

    申请号：US12787128

    申请日：2010-05-25

    申请人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    发明人： Michael K. Gschwind ,  John K. O'Brien ,  Valentina Salapura ,  Zehra N. Sura

    IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F9/30

    CPC分类号： G06F9/544

    摘要： This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated hardware buffer as an intermediary storage for transferring values from registers in one thread to registers in another thread. The method may provide a generic, programmable solution that can transfer any subset of register values between threads in any given order, where the source and target registers may or may not be correlated. The method also may allow for determinate access times, since it completely bypasses the memory hierarchy. Also, the method is designed to be lightweight, focusing on communication, and keeping synchronization facilities orthogonal to the communication mechanism. It may be used by a helper thread that performs data prefetching for an application thread, for example, to initialize the upward-exposed reads in the address computation slice of the helper thread code.

    摘要翻译： 本公开描述了一种方法和系统，其可以实现线程之间的值的快速，硬件辅助，生产者 - 消费者风格的通信。 该方法在一个方面中使用专用硬件缓冲器作为用于将值从一个线程中的寄存器传送到另一线程中的寄存器的中间存储器。 该方法可以提供通用的可编程解决方案，其可以以任何给定的顺序在线程之间传送寄存器值的任何子集，其中源寄存器和目标寄存器可以或可以不相关。 该方法还可以允许确定的访问时间，因为它完全绕过存储器层次结构。 此外，该方法被设计为轻量级，专注于通信，并保持与通信机制正交的同步设备。 它可以由对应用程序线程执行数据预取的辅助线程使用，例如，初始化辅助线程代码的地址计算切片中的向上暴露的读取。

    Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching
    7.
    发明授权
    Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching 有权
    结合预解码时间优化指令序列缓存执行预解码时间优化指令

    公开(公告)号：US09354888B2

    公开(公告)日：2016-05-31

    申请号：US13432357

    申请日：2012-03-28

    申请人： Michael K. Gschwind ,  Valentina Salapura

    发明人： Michael K. Gschwind ,  Valentina Salapura

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/384

    摘要： A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.

    摘要翻译： 一种执行预解码时间优化指令并结合预解码时间优化指令序列缓存的方法。 该方法包括接收指令序列的第一指令和指令序列的第二指令，并且确定是否可以优化第一指令和第二指令。 响应于确定可以优化第一指令和第二指令，该方法包括：对指令序列执行预解码优化并产生新的第二指令，其中新的第二指令不依赖于目标操作数 所述第一指令并将预解码的第一指令和预解码的新的第二指令存储在指令高速缓存中。 响应于确定第一指令和第二指令不能被优化，该方法包括：将预解码的第一指令和预解码的第二指令存储在指令高速缓存中。

    Using register last use infomation to perform decode-time computer instruction optimization
    8.
    发明授权
    Using register last use infomation to perform decode-time computer instruction optimization 有权
    使用寄存器最后使用信息执行解码时间计算机指令优化

    公开(公告)号：US09286072B2

    公开(公告)日：2016-03-15

    申请号：US13251486

    申请日：2011-10-03

    申请人： Michael K. Gschwind ,  Valentina Salapura

    发明人： Michael K. Gschwind ,  Valentina Salapura

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30181 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3851

    摘要： Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified as a last-use register, where a last-use register has a value that is not to be accessed by later instructions, whereby the two computer machine instructions are replaced by a single optimized internal instruction for execution, the single optimized instruction not including the last-use register.

    摘要翻译： 两台计算机机器指令被取出执行，而被一个要执行的优化指令所代替，其中由两个指令使用的临时寄存器被识别为最后使用寄存器，其中最后使用寄存器的值不是 由后来的指令访问，由此两个计算机机器指令被用于执行的单个优化的内部指令代替，单个优化的指令不包括最后使用的寄存器。

    Using Register Last Use Infomation to Perform Decode-Time Computer Instruction Optimization
    9.
    发明申请
    Using Register Last Use Infomation to Perform Decode-Time Computer Instruction Optimization 有权
    使用注册最后使用信息执行解码时间计算机指令优化

    公开(公告)号：US20130086368A1

    公开(公告)日：2013-04-04

    申请号：US13251486

    申请日：2011-10-03

    申请人： Michael K. Gschwind ,  Valentina Salapura

    发明人： Michael K. Gschwind ,  Valentina Salapura

    IPC分类号： G06F9/318

    CPC分类号： G06F9/30181 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3851

    摘要： Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified as a last-use register, where a last-use register has a value that is not to be accessed by later instructions, whereby the two computer machine instructions are replaced by a single optimized internal instruction for execution, the single optimized instruction not including the last-use register.

    摘要翻译： 两台计算机机器指令被取出执行，而被一个要执行的优化指令所代替，其中由两个指令使用的临时寄存器被识别为最后使用寄存器，其中最后使用寄存器的值不是 由后来的指令访问，由此两个计算机机器指令被用于执行的单个优化的内部指令代替，单个优化的指令不包括最后使用的寄存器。

    Exploiting an Architected List-Use Operand Indication in a Computer System Operand Resource Pool
    10.
    发明申请
    Exploiting an Architected List-Use Operand Indication in a Computer System Operand Resource Pool 有权
    在计算机系统操作数资源池中利用架构化的列表使用操作数指示

    公开(公告)号：US20130086365A1

    公开(公告)日：2013-04-04

    申请号：US13251519

    申请日：2011-10-03

    申请人： Michael K. Gschwind ,  Valentina Salapura

    发明人： Michael K. Gschwind ,  Valentina Salapura

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30072 ,  G06F9/30138 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3859

    摘要： A pool of available physical registers are provided for architected registers, wherein operations are performed that activate and deactivate selected architected registers, such that the deactivated selected architected registers need not retain values, and physical registers can be deallocated to the pool, wherein deallocation of physical registers is performed after a last-use by a designated last-use instruction, wherein the last-use information is provided either by the last-use instruction or a prefix instruction, wherein reads to deallocated architecture registers return an architected default value.

    摘要翻译： 为架构化寄存器提供可用物理寄存器池，其中执行激活和去激活所选择的架构化寄存器的操作，使得停用的所选建筑寄存器不需要保留值，并且物理寄存器可以被释放到池中，其中物理 寄存器在最后使用指定的最后使用指令之后执行，其中最后使用信息由最后使用指令或前缀指令提供，其中对解除分配的体系结构寄存器的读取返回架构的默认值。