公开(公告)号：US06362055B1

公开(公告)日：2002-03-26

申请号：US09144527

申请日：1998-08-31

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L218234

Abstract: A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

公开(公告)号：US06361874B1

公开(公告)日：2002-03-26

申请号：US09597623

申请日：2000-06-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6659 ,  Y10T428/31906

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-15 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。 该技术产生了300nm厚的浅非晶区和深非晶区。 浅非晶区域可以在衬底的顶表面之下10-15nm之间，并且深非晶区域可以在衬底顶表面之下的150-200nm之间。 该过程可以减少栅极过熔效应。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。

公开(公告)号：US06339017B1

公开(公告)日：2002-01-15

申请号：US09596993

申请日：2000-06-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L214763

CPC classification number: H01L29/6659 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/7833

Abstract: A method of manufacturing small structures or narrow structures on an ultra-large scale integrated circuit utilizes a hard mask. A mask layer can be deposited over a top surface of a material above a semiconductor substrate. A mask layer can be lithographically patterned to have a feature. The side walls of the feature can be oxidized. The oxidized side walls can be removed to reduce the size of the feature below one lithographic feature. The material underneath mask layer can be etched in accordance with the feature without the oxidized side walls.

Abstract translation: 在超大规模集成电路上制造小结构或窄结构的方法利用硬掩模。 掩模层可沉积在半导体衬底上方的材料的顶表面上。 掩模层可以光刻图案化以具有特征。 特征的侧壁可以被氧化。 可以去除氧化的侧壁以将特征的尺寸减小到低于一个光刻特征。 掩模层下面的材料可以根据没有氧化侧壁的特征进行蚀刻。

公开(公告)号：US06297117B1

公开(公告)日：2001-10-02

申请号：US09781389

申请日：2001-02-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1083 ,  Y10S977/888

Abstract: Halo regions are formed for a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate. A first dummy spacer is formed on a first sidewall, and a second dummy spacer is formed on a second sidewall, of the gate structure and the gate dielectric. The first dummy spacer is disposed substantially over a drain extension junction, and the second dummy spacer is disposed substantially over a source extension junction of the field effect transistor. An insulating material is deposited to cover the first dummy spacer, the second dummy spacer, and the gate structure. The insulating material is polished down such that the top surfaces of the gate structure, the first dummy spacer, and the second dummy spacer are exposed and are level with a top surface of the insulating material. The first dummy spacer is etched away to form a first spacer opening, and the second dummy spacer is etched away to form a second spacer opening. A halo dopant is implanted through the first spacer opening to form a drain halo region substantially only beneath the drain extension junction within the semiconductor substrate and through the second spacer opening to form a source halo region substantially only beneath the source extension junction within the semiconductor substrate. The drain halo region and the source halo region are heated up in a thermal anneal process, such as a (LTP) laser thermal process, to activate the halo dopant substantially only within the drain halo region and the source halo region. An amorphization dopant may also be implanted into the drain halo region and the source halo region for activating the halo dopant within the drain and source halo regions at a lower temperature.

Abstract translation: 为半导体衬底的有源器件区域内的栅极电介质上具有栅极结构的场效应晶体管形成光晕区域。 第一虚拟间隔物形成在第一侧壁上，并且第二虚设间隔物形成在栅极结构和栅极电介质的第二侧壁上。 第一虚拟间隔物基本上设置在漏极延伸结上方，并且第二虚拟间隔物基本上设置在场效应晶体管的源极延伸结上。 沉积绝缘材料以覆盖第一虚拟间隔物，第二虚拟间隔物和栅极结构。 绝缘材料被抛光，使得栅极结构的顶表面，第一虚设衬垫和第二虚拟衬垫露出并与绝缘材料的顶表面平齐。 蚀刻掉第一虚拟间隔物以形成第一间隔开口，并且蚀刻掉第二虚拟间隔物以形成第二间隔开口。 通过第一间隔开口注入卤素掺杂剂，以形成基本上仅在半导体衬底内的漏极延伸结下方的漏极晕区，并通过第二间隔开口，以形成基本上仅在半导体衬底内的源极延伸结下方的源极晕区 。 在诸如（LTP）激光热处理的热退火工艺中，将漏极晕区域和源极晕区域加热，以基本上仅在漏极晕区域和源极晕区域内激活卤素掺杂物。 也可以将非晶化掺杂剂注入到漏极卤素区域和源极晕区域中，以在较低温度下激活漏极和源极区域内的卤素掺杂剂。

公开(公告)号：US06287925B1

公开(公告)日：2001-09-11

申请号：US09512202

申请日：2000-02-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: For forming a highly conductive junction in an active device area of a semiconductor substrate, a first dopant is implanted into the active device area to form a preamorphization region. A second dopant is then implanted into the preamorphization region to have a dopant profile along a depth of the preamorphization region, and the dopant profile has a dopant peak within the preamorphization region. A RTA (Rapid Thermal Anneal) is performed to recrystallize a portion of the preamorphization region from an interface between the preamorphization region and the semiconductor substrate to below the dopant peak. A LTP (Laser Thermal Process) is then performed to recrystallize a remaining portion of the preamorphization region that has not been recrystallized during the RTA (Rapid Thermal Anneal) to activate a substantial portion of the second dopant in the preamorphization region. In this manner, a relatively small portion of junction at the interface of the junction with the semiconductor substrate is recrystallized using a RTA (Rapid Thermal Anneal) process before the LTP (Laser Thermal Process). The interface of the junction with the semiconductor substrate that is recrystallized using a RTA (Rapid Thermal Anneal) has a minimized amount of crystallization defects such that the resistance of the junction is minimized. Such a highly conductive junction may be formed as a drain extension, a source extension, a drain contact junction, and a source contact junction of a field effect transistor for minimizing the series resistance at the drain and source of the field effect transistor and thus for enhancing the speed performance of the field effect transistor.

Abstract translation: 为了在半导体衬底的有源器件区域中形成高导电结，将第一掺杂剂注入有源器件区域以形成预变形区域。 然后将第二掺杂剂注入到预变质区域中以沿着预变质区域的深度具有掺杂剂分布，并且掺杂剂分布在预变形区域内具有掺杂剂峰。 进行RTA（快速热退火）以使前变质区域的一部分从前变质区域和半导体衬底之间的界面重结晶到掺杂剂峰值以下。 然后进行LTP（激光热处理）以使在RTA（快速热退火）期间未重结晶的剩余部分再结晶，以激活前变质区域中的大部分第二掺杂剂。 以这种方式，在LTP（激光热处理）之前，使用RTA（快速热退火）工艺在与半导体衬底的结的界面处的相交处相对小的部分进行再结晶。 使用RTA（快速热退火）重结晶的与半导体衬底的结的界面具有最小量的结晶缺陷，使得结的电阻最小化。 这种高导电结可以形成为场效应晶体管的漏极延伸，源极延伸，漏极接触结和源极接触结，用于使场效应晶体管的漏极和源极处的串联电阻最小化， 提高了场效应晶体管的速度性能。

公开(公告)号：US06284672B1

公开(公告)日：2001-09-04

申请号：US09260255

申请日：1999-03-02

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21302

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/306

Abstract: A method of manufacturing an integrated circuit is disclosed herein. The method includes providing an implant in a semiconductor to create an amorphous region; growing a thermal oxide layer on the amorphous region such that the thermal oxide layer consumes a portion of the amorphous region; and removing the thermal oxide layer such that the resulting amorphous region is super-shallow.

Abstract translation: 本文公开了一种制造集成电路的方法。 该方法包括在半导体中提供植入物以产生非晶区域; 在非晶区域上生长热氧化物层，使得热氧化物层消耗非晶区域的一部分; 并且去除热氧化物层，使得所得到的非晶区域是超浅的。

公开(公告)号：US06274469B1

公开(公告)日：2001-08-14

申请号：US09490805

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21338

CPC classification number: H01L29/66583 ,  H01L21/0337 ,  H01L21/28123 ,  H01L29/6659

Abstract: A method of fabricating an integrated circuit with a gate structure comprised of an oxide/polysilicon/metal stack. The method includes forming the gate structure by using a metal plug as a hard mask in place of a hard mask produced using photolithography. Thus, linewidth limitations of conventional photolithography do not apply. Specifically, the method includes providing a pattern over a semiconductor substrate; partially filling the pattern with a polysilicon material such that a trench is left in the polysilicon material, and filling the trench in the polysilicon material with metal to form a plug. After forming the materials, excess materials are removed leaving the gate structure.

Abstract translation: 一种制造具有由氧化物/多晶硅/金属堆叠构成的栅极结构的集成电路的方法。 该方法包括通过使用金属塞作为硬掩模来代替使用光刻产生的硬掩模来形成栅极结构。 因此，常规光刻的线宽限制不适用。 具体地，该方法包括在半导体衬底上提供图案; 部分地用多晶硅材料填充图案，使得沟槽留在多晶硅材料中，并用金属填充多晶硅材料中的沟槽以形成插头。 在形成材料之后，去除留下栅极结构的多余材料。

公开(公告)号：US06255175B1

公开(公告)日：2001-07-03

申请号：US09479552

申请日：2000-01-07

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28052 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659 ,  Y10S977/707

Abstract: A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region at the sidewalls of the gate structure is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap.

Abstract translation: 制造场效应晶体管以具有漏极重叠和源重叠，以使栅极和漏极之间以及场效应晶体管的栅极和源极之间的串联电阻最小化。 通过在场效应晶体管的栅极结构的侧壁处形成耗尽区，减少由漏极重叠和源极重叠形成的寄生米勒电容。 通过对栅极结构的侧壁进行反掺杂来形成栅极结构的侧壁处的耗尽区。 在场效应晶体管的漏极侧和源极侧的栅极结构的侧壁掺杂有与栅极结构内的掺杂剂类型相反的掺杂剂。 在栅极结构的侧壁处的这种掺杂剂从侧壁形成相应的耗尽区，从而在栅极结构下延伸的漏极重叠和源极重叠的大致边缘，以减小由漏极重叠和源极重叠形成的寄生米勒电容。

公开(公告)号：US06251757B1

公开(公告)日：2001-06-26

申请号：US09512201

申请日：2000-02-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324

Abstract: In a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predetermined depth from the predetermined surface of the semiconductor substrate. Furthermore, a second dopant is implanted into the preamorphization junction with a dopant profile along a depth of the semiconductor substrate from the predetermined surface of the semiconductor substrate. A peak of the dopant profile is located at a fraction of the first predetermined depth of the preamorphization junction. A silicidation RTA (Rapid Thermal Anneal) is performed to form silicide on the semiconductor substrate. The silicidation RTA (Rapid Thermal Anneal) recrystallizes the preamorphization junction from the first predetermined depth of the preamorphization junction up to an unrecrystallized depth of the preamorphization junction. The unrecrystallized depth of the preamorphization junction does not reach up to the peak of the dopant profile. An additional RTA (Rapid Thermal Anneal) is performed to recrystallize the preamorphization junction from the unrecrystallized depth of the preamorphization junction substantially up to the predetermined surface of the semiconductor substrate. The highly activated shallow abrupt doped junction is formed by activation of a substantial portion of the second dopant in the preamorphization junction during the additional RTA (Rapid Thermal Anneal).

Abstract translation: 在半导体衬底中制造高激活浅突变掺杂结的方法中，将第一掺杂剂注入到半导体衬底的预定表面中以形成从半导体衬底的预定表面具有第一预定深度的预变形结。 此外，第二掺杂剂从半导体衬底的预定表面沿着半导体衬底的深度注入到具有掺杂剂分布的前变质结内。 掺杂剂分布的峰位于预变形结的第一预定深度的一部分。 进行硅化RTA（快速热退火）以在半导体衬底上形成硅化物。 硅化RTA（快速热退火）使从前变质结的第一预定深度到预变形结的未再结晶深度的预变形结重结晶。 预变形结的未再结晶深度未达到掺杂剂分布的峰值。 进行另外的RTA（快速热退火）以使从前变质结的未再结晶深度基本上直到半导体衬底的预定表面重结晶前变质结。 在额外的RTA（快速热退火）期间，通过在预变形结中活化大部分第二掺杂剂来形成高活化的浅突变掺杂结。

公开(公告)号：US06235599B1

公开(公告)日：2001-05-22

申请号：US09426402

申请日：1999-10-25

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L29/6659

Abstract: A shallow doped junction that is part of an integrated circuit device within a semiconductor substrate is formed with box-shaped implant profiles for implantation of the amorphizing implant species and the dopant implant species such that the doped junction has minimized sheet resistance. A box-shaped implant profile for implantation of the amorphizing implant species is formed from implantation of the amorphizing implant species with a plurality of projection ranges to form a plurality of implant profiles. A box-shaped implant profile for implantation of the dopant implant species is formed from implantation of the dopant implant species with a plurality of projection ranges to form a plurality of implant profiles. In addition, each of the plurality of implant profiles for the dopant implant species is preferably below the solid solubility of the dopant implant species within the semiconductor substrate. By controlling the implant profiles of the amorphizing implant species and the dopant implant species during fabrication of the doped junction, the sheet resistance of the doped junction is minimized. In addition, the temperature and the time period for activating the dopant implant species in a RTA (Rapid Thermal Anneal) process is also minimized such that the doped junction remains relatively shallow.

Abstract translation: 作为半导体衬底内的集成电路器件的一部分的浅掺杂结形成有用于注入非晶化注入物种和掺杂剂注入物种的盒形注入轮廓，使得掺杂结具有最小的薄层电阻。 用于植入非晶化植入物种的盒形植入物轮廓通过用多个投影范围的植入非晶化植入物种形成，以形成多个植入物轮廓。 通过用多个投影范围注入掺杂剂注入物种来形成用于注入掺杂剂注入种类的盒状植入物轮廓，以形成多个植入物轮廓。 此外，用于掺杂剂注入物种的多个植入物轮廓中的每一个优选低于半导体衬底内的掺杂剂注入种类的固体溶解度。 通过在掺杂结的制造过程中控制非晶化注入物种和掺杂剂注入物种的种植体轮廓，掺杂结的薄层电阻最小化。 此外，在RTA（快速热退火）工艺中激活掺杂剂注入物质的温度和时间段也被最小化，使得掺杂的结保持相对较浅。