公开(公告)号：US20070283316A1

公开(公告)日：2007-12-06

申请号：US11420941

申请日：2006-05-30

申请人： Robert E. Stengel

发明人： Robert E. Stengel

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F1/025 ,  H03K5/131 ,  H03K2005/00045

摘要： A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

摘要翻译： 与本发明的某些实施例一致的信号发生器具有产生周期性的参考时钟输出脉冲序列的参考时钟（34）。 窗口产生器（38）产生多个时间窗口，所选择的多个参考时钟输出脉冲通过该时间窗口被选择性地作为窗口脉冲通过，使得窗口脉冲形成选定的脉冲图案。 可编程延迟（46）具有延迟分辨率，其延迟时间比时钟输出脉冲的周期更精细。 可编程延迟（46）将每个加窗脉冲延迟编程的延迟时间，从而为加窗脉冲提供定时校正，以产生脉冲的输出模式。

公开(公告)号：US07254208B2

公开(公告)日：2007-08-07

申请号：US10441333

申请日：2003-05-20

申请人： Andrew Tomerlin ,  Robert E. Stengel

发明人： Andrew Tomerlin ,  Robert E. Stengel

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03K3/84 ,  H03K5/00006 ,  H03K5/1504 ,  H03L7/0812 ,  H04B1/707 ,  H04B2201/70707

摘要： A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, . . . , 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of FREF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

摘要翻译： 与本发明的某些实施例一致的频率扩展电路具有具有多个抽头的第一延迟线（108）。 延迟线在时钟速率为F REF REF的输入端接收参考时钟。 第二延迟线（104,150）还在输入端接收参考时钟。 逻辑电路（130,134，...，138,140）将来自第一延迟线（108）的延迟线抽头的信号与来自第二和/或第一延迟线（104，...）的延迟线抽头的信号相结合， 150，108），以产生具有组合时钟速率为F×REF×2N的时钟脉冲的集合。 使用延迟锁定环路，至少一个延迟线可以锁定到参考时钟。 时钟脉冲可以与种子寄存器（204）内容逻辑地组合以产生递归序列或用于卷积编码的数据，或者与用于CDMA收发器中的相关的导频数据相结合。

公开(公告)号：US07114069B2

公开(公告)日：2006-09-26

申请号：US10420221

申请日：2003-04-22

申请人： Andrew Tomerlin ,  Nicholas Giovanni Cafaro ,  Robert E. Stengel

发明人： Andrew Tomerlin ,  Nicholas Giovanni Cafaro ,  Robert E. Stengel

IPC分类号： G06F9/00

CPC分类号： G06F15/7867 ,  G06F1/08 ,  Y02D10/12 ,  Y02D10/13

摘要： A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks (208), wherein certain of the configurable circuit blocks (208) comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor (218) configures a function of a plurality of the configurable circuit blocks. A memory (224) stores program instructions used by the control processor (218). A multiple frequency generator (230) receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (218). A timing control circuit (236) receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit (236) operates under control of the control processor (218).

摘要翻译： 与本发明的某些实施例一致的可重构处理器电路（200）具有可配置电路块（208）的阵列，其中某些可配置电路块（208）包括可配置的算术逻辑单元和时钟数字逻辑电路之一。 控制处理器（218）配置多个可配置电路块的功能。 存储器（224）存储由控制处理器（218）使用的程序指令。 多频发生器（230）接收参考时钟并从其合成多个时钟信号，每个时钟信号由控制处理器（218）频率配置。 定时控制电路（236）接收多个时钟信号，在多个电路块中分配不同频率的多个时钟信号，并将时钟信号发送到电路块，其中定时控制电路（236）在控制下工作 的控制处理器（218）。

公开(公告)号：US06867736B2

公开(公告)日：2005-03-15

申请号：US10291306

申请日：2002-11-08

申请人： Antonio Faraone ,  Robert E. Stengel ,  Carlo Di Nallo

发明人： Antonio Faraone ,  Robert E. Stengel ,  Carlo Di Nallo

IPC分类号： H01Q1/38 ,  H01Q1/48 ,  H01Q5/00 ,  H01Q5/357 ,  H01Q9/42

CPC分类号： H01Q9/42 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q5/357

摘要： Multi-band antenna systems (116, 1100,1200) for wireless communication devices (100) for use in wireless communications systems (1300) are disclosed. The multi-band antennas systems include a conductive film (204, 1104, 1204) that include ground plane areas (206, 1106, 1206) and conductive traces (208, 1108, 1208) that substantially circumscribe areas that include a plurality of interconnected swaths (222-230, 1116-1120, 1216-1220). The antenna systems are capable of operating in a first common mode for supporting communications in a first frequency band, and in a second common mode and differential mode for supporting communications in a second frequency band. Nulls of gain patterns of the second common and differential mode are offset, such that sum of the gain patterns does not include nulls.

摘要翻译： 公开了一种用于无线通信系统（1300）中的无线通信设备（100）的多频带天线系统（116,111,1200）。 多频带天线系统包括导电膜（204,1104,1204），其包括接地平面区域（206,1106,1206）和导电迹线（208,1108,1208），导电迹线基本上限定包括多个相互连接的条带 （222-230,1116-1120,1216-1220）。 天线系统能够以第一共同模式操作，用于支持第一频带中的通信，以及用于支持第二频带中的通信的第二共模和差分模式。 第二公共和差分模式的增益模式的空值被偏移，使得增益模式的和不包括空值。

公开(公告)号：US06794913B1

公开(公告)日：2004-09-21

申请号：US10447443

申请日：2003-05-29

申请人： Robert E. Stengel

发明人： Robert E. Stengel

IPC分类号： H03L706

CPC分类号： H03L7/087 ,  H03L7/0814 ,  H03L7/0818

摘要： A delay locked loop circuit 300 consistent with certain embodiments of the present invention has a delay line 304 with coarse adjustment 322 and fine adjustment 360 inputs. The coarse adjustment input 322 provides an overall adjustment of all of the delay line's delay elements while the fine adjustment inputs 360 permit adjusting the individual delay value of each delay element. A first multiplexer 330 receives the delay tap outputs and produces a first selected output while a second multiplexer 334 also receives the delay tap outputs and produces a second selected output. A measurement circuit 344 measures a difference between the first and second output as a measurement of a selected delay element's delay value. An error calculator 346 receives the output of the measurement circuit and calculates fine adjustment voltages for each of the selected delay elements. A tuning circuit 350 applies the fine adjustment voltages to the fine adjustment inputs of the delay line 304.

摘要翻译： 与本发明的某些实施例一致的延迟锁定环电路300具有粗略调整322和微调360输入的延迟线304。 粗调输入322提供所有延迟线的延迟元件的总体调整，而微调输入360允许调整每个延迟元件的各个延迟值。 第一多路复用器330接收延迟抽头输出并产生第一选择输出，而第二多路复用器334还接收延迟抽头输出并产生第二选择的输出。 测量电路344测量第一和第二输出之间的差作为所选择的延迟元件的延迟值的测量值。 误差计算器346接收测量电路的输出，并计算每个所选择的延迟元件的微调电压。 调谐电路350将微调电压施加到延迟线304的微调输入端。

公开(公告)号：US06573792B1

公开(公告)日：2003-06-03

申请号：US10017984

申请日：2001-12-13

申请人： Scott A. Olson ,  Robert E. Stengel

发明人： Scott A. Olson ,  Robert E. Stengel

IPC分类号： H03F100

CPC分类号： H03F1/3229

摘要： A feedforward amplifier (150) according to the present invention uses a direct coupling of an amplifier stage (158) with the amplifier's load (RL). The main amplifier (202) is coupled through a transmission line (210) to the load. This direct coupled amplifier stage (158) is driven by a signal that induces a very low impedance in parallel with the load to the error signal, but appears as an open circuit to the desired signal so that the desired signal from the main amplifier is substantially unaffected.

摘要翻译： 根据本发明的前馈放大器（150）使用放大器级（158）与放大器的负载（RL）的直接耦合。 主放大器（202）通过传输线（210）耦合到负载。 该直接耦合放大器级158由一个信号驱动，该信号引起与该误差信号的负载并联的非常低的阻抗，但是作为对所需信号的开路呈现，使得来自主放大器的所需信号基本上 不受影响

公开(公告)号：US06356149B1

公开(公告)日：2002-03-12

申请号：US09546618

申请日：2000-04-10

申请人： Robert E. Stengel ,  Wang-Chang Albert Gu

发明人： Robert E. Stengel ,  Wang-Chang Albert Gu

IPC分类号： H03F368

CPC分类号： H03F1/0288 ,  H03H5/12 ,  H03H7/20

摘要： A tunable inductor circuit and phase tuning circuit utilizing a tunable inductor circuit for dynamically controlling signal phase delay in RF/Microwave Circuits and related applications. The tunable inductor includes an inductor and a voltage variable capacitor connected to each other. The tunable inductor and voltage variable capacitor can be connected to each other in parallel or in series. The phase tuning circuit includes at least one tunable inductor circuit and at least one voltage variable capacitor coupled to the at least one tunable inductor circuit, wherein the at least one tunable inductor circuit and the voltage variable capacitor are responsive to control signals to alter a tuning characteristic of the phase tuning circuit.

摘要翻译： 一种可调谐电感电路和相位调谐电路，利用可调谐电感电路来动态控制RF /微波电路及相关应用中的信号相位延迟。 可调电感器包括彼此连接的电感器和电压可变电容器。 可调谐电感器和电压可变电容器可以并联或串联连接。 相位调谐电路包括至少一个可调电感器电路和耦合到该至少一个可调电感器电路的至少一个电压可变电容器，其中至少一个可调谐电感器电路和电压可变电容器响应于控制信号来改变调谐 相位调谐电路的特性。

公开(公告)号：US5901346A

公开(公告)日：1999-05-04

申请号：US773798

申请日：1996-12-17

申请人： Robert E. Stengel ,  Scott A. Olson

发明人： Robert E. Stengel ,  Scott A. Olson

IPC分类号： H03F1/02 ,  H03F1/32 ,  H04L27/36 ,  H04B1/04

CPC分类号： H03F1/0294 ,  H03F1/3247 ,  H03F1/3294 ,  H04L27/367 ,  H03F2201/3233

摘要： A compensated signal source (210, 220) utilizes baseband signals and a radio frequency carrier signal to generate a set of source output signals (226, 227) which are coupled to a particular circuit (230, 240, 250). The signal source (210, 220) is operable in a characterizing mode in which a test configuration is applied, and outputs from the signal source and the particular circuit measured to develop parameters representing imperfections within the signal source and within the particular circuit. The signal source (210, 220) is operable in a normal mode, in which compensation based on the measured parameters is applied to account for the imperfections. In a preferred embodiment, the particular circuit (230, 240, 250) and compensated signal source (210, 220) form part of an amplifier (200) that implements linear amplification using nonlinear components (LINC) techniques.

摘要翻译： 补偿信号源（210,220）利用基带信号和射频载波信号来产生耦合到特定电路（230,240,250）的一组源输出信号（226,227）。 信号源（210,220）可以在其中应用测试配置的特征模式中操作，并且测量信号源和特定电路的输出，以产生表示信号源内和特定电路内的缺陷的参数。 信号源（210,220）可以在正常模式下操作，其中应用基于所测量的参数的补偿来解释缺陷。 在优选实施例中，特定电路（230,240,250）和补偿信号源（210,220）形成使用非线性分量（LINC）技术实现线性放大的放大器（200）的一部分。

公开(公告)号：US5506493A

公开(公告)日：1996-04-09

申请号：US402242

申请日：1995-03-10

申请人： Robert E. Stengel

发明人： Robert E. Stengel

IPC分类号： H02M3/158 ,  H02M7/48 ,  H03F1/02 ,  H03F3/217 ,  G05F1/613

CPC分类号： H03F3/2173 ,  H02M3/158 ,  H02M7/483 ,  H03F1/0227

摘要： A voltage regulator (200) includes a controller (204) which selectively activates a plurality of switching means (208, 210, 214, and 212) in order to select between a first current loop in which an energy storage device is charged by an input supply and a second loop in which the energy storage device is coupled to the output terminal (242) of the regulator (200). The switching from the second current loop to the first is governed by the controller (204) determining that the loop current in the second loop has reached a predetermined level. A first switching audio amplifier (300) is disclosed which uses the voltage regulator (200) to provide a continuously variable output voltage (318) in order to provide for high quality amplification which is independent of the volume setting. A second audio amplifier (400) includes a converter (436) which provides discrete voltage levels to a full wave bridge in order to provide improved audio output.

摘要翻译： 电压调节器（200）包括控制器（204），其选择性地激活多个开关装置（208,210,214和212），以便在第一电流回路中选择能量存储装置由输入端 电源和第二回路，其中能量存储装置耦合到调节器（200）的输出端子（242）。 从第二电流回路切换到第一电流回路由控制器（204）决定第二回路中的回路电流已经达到预定水平。 公开了一种第一开关音频放大器（300），其使用电压调节器（200）来提供连续可变的输出电压（318），以便提供与音量设置无关的高质量放大。 第二音频放大器（400）包括向全波桥提供离散电压电平的转换器（436），以便提供改进的音频输出。

公开(公告)号：US5442317A

公开(公告)日：1995-08-15

申请号：US402759

申请日：1995-03-10

申请人： Robert E. Stengel

发明人： Robert E. Stengel

IPC分类号： H02M3/158 ,  H02M7/48 ,  H02M7/483 ,  H03F1/02 ,  H03F3/217 ,  H03F3/38

CPC分类号： H03F3/2173 ,  H02M3/158 ,  H02M7/483 ,  H03F1/0227 ,  H03F2200/351

摘要： A voltage regulator (200) includes a controller (204) which selectively activates a plurality of switching means (208, 210, 214, and 212) in order to select between a first current loop in which an energy storage device is charged by an input supply and a second loop in which the energy storage device is coupled to the output terminal (242) of the regulator (200). The switching from the second current loop to the first is governed by the controller (204) determining that the loop current in the second loop has reached a predetermined level. A first switching audio amplifier (300) is disclosed which uses the voltage regulator (200) to provide a continuously variable output voltage (318) in order to provide for high quality amplification which is independent of the volume setting. A second audio amplifier (400)includes a converter (436) which provides discrete voltage levels to a full wave bridge in order to provide improved audio output.

摘要翻译： 电压调节器（200）包括控制器（204），其选择性地激活多个开关装置（208,210,214和212），以便在第一电流回路中选择能量存储装置由输入端 电源和第二回路，其中能量存储装置耦合到调节器（200）的输出端子（242）。 从第二电流回路切换到第一电流回路由控制器（204）决定第二回路中的回路电流已经达到预定水平。 公开了一种第一开关音频放大器（300），其使用电压调节器（200）来提供连续可变的输出电压（318），以便提供与音量设置无关的高质量放大。 第二音频放大器（400）包括向全波桥提供离散电压电平的转换器（436），以便提供改进的音频输出。