公开(公告)号：US06882182B1

公开(公告)日：2005-04-19

申请号：US10669589

申请日：2003-09-23

申请人： Robert O. Conn ,  Gary R. Lawman ,  Christopher H. Kingsley ,  Austin H. Lesea

发明人： Robert O. Conn ,  Gary R. Lawman ,  Christopher H. Kingsley ,  Austin H. Lesea

IPC分类号： G06F1/10 ,  H03K3/012 ,  H03K19/00

CPC分类号： G06F1/10 ,  H03K3/012

摘要： A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.

摘要翻译： 可调谐时钟分配系统用于最小化集成电路中时钟分配网络的功耗。 可调时钟分配系统在时钟分配网络上提供可调电感，以调节可调时钟分配系统中的谐振频率。 调谐电感使得可调谐时钟分配系统的谐振频率接近时钟分配网络上时钟信号的频率。 随着可调谐时钟分配系统的谐振频率接近时钟信号的频率，时钟分配网络的功耗降低。 一些实施例还在时钟分配网络上提供可调谐电容以调节可调时钟分配系统的谐振频率。

公开(公告)号：US06864142B1

公开(公告)日：2005-03-08

申请号：US10079235

申请日：2002-02-19

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L21/268 ,  H01L21/8246 ,  H01L27/112 ,  H01L21/336 ,  H01L21/30 ,  H01L21/326 ,  H01L21/8236

CPC分类号： H01L27/1126 ,  H01L21/268 ,  H01L27/112

摘要： A method for programming a semiconductor element in a semiconductor structure such as an IC involves reducing the backside thickness of the substrate and directing an energy beam through the backside at an opaque component of the semiconductor element. A support structure mounted on the semiconductor structure provides support during and after the thinning operation. Alternatively, the substrate can be thinned only under the semiconductor element, leaving the rest of the substrate thick enough to maintain structural integrity. The energy beam heats the opaque component. The prior thinning operation minimizes heat dissipation away from the semiconductor element, so that dopant diffusion occurs, changing the electrical characteristics of the semiconductor element. By modifying selected elements in this manner, a semiconductor structure can be permanently programmed, even if it does not include non-volatile memory. Additionally, security is enhanced since the programming leaves no visible signs.

摘要翻译： 用于对诸如IC的半导体结构中的半导体元件进行编程的方法包括减小衬底的背面厚度并且将能量束引导通过半导体元件的不透明部件的背面。 安装在半导体结构上的支撑结构在稀化操作期间和之后提供支撑。 或者，衬底可以仅在半导体元件下方变薄，使得衬底的其余部分足够厚以保持结构完整性。 能量束加热不透明组分。 现有的稀疏操作使得远离半导体元件的散热最小化，从而发生掺杂剂扩散，改变半导体元件的电特性。 通过以这种方式修改所选择的元件，即使不包括非易失性存储器，半导体结构也可被永久编程。 此外，安全性得到增强，因为编程没有留下可见的迹象。

公开(公告)号：US06815973B1

公开(公告)日：2004-11-09

申请号：US10461284

申请日：2003-06-13

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： G01R3126

CPC分类号： G01R31/311 ,  G01R31/2884 ,  G01R31/31728 ,  G01R31/318511

摘要： A wafer of integrated circuits under test (ICUT) is tested by supplying power to the ICUTs using power and ground traces that extend between rows of the ICUTs in scribe streets. Test information is supplied to each ICUT by transmitting the test information optically onto the entire wafer. A diode on each ICUT receives the optical test information. The ICUT uses the test information to perform a self-test. Each ICUT has a diode for transmitting optical test information. All ICUTs on the wafer transmit results of the self-tests at the same time. A test device receives the optical test information and identifies the information from each of the many ICUTs, one from another. An entire wafer of ICUTs is therefore tested simultaneously without using a probe card either to power an ICUT or to supply test information to or receive test information from an ICUT.

摘要翻译： 通过使用在划线路上的ICUT的行之间延伸的电源和接地迹线向ICUT供电来测试正在测试的集成电路（ICUT）的晶片。 通过将测试信息光学发送到整个晶片上，将测试信息提供给每个ICUT。 每个ICUT上的二极管接收光学测试信息。 ICUT使用测试信息执行自检。 每个ICUT都有一个用于传输光学测试信息的二极管。 晶圆上的所有ICUT同时传输自检的结果。 测试设备接收光学测试信息并且从多个ICUT中的每一个识别来自另一个的信息。 因此，不需要使用探针卡来为ICUT供电或向ICUT提供测试信息或从ICUT接收测试信息，因此整个ICUT的整个晶片都将被同时测试。

公开(公告)号：US06611477B1

公开(公告)日：2003-08-26

申请号：US10132419

申请日：2002-04-24

申请人： Gil A. Speyer ,  David L. Ferguson ,  Daniel Y. Chung ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

发明人： Gil A. Speyer ,  David L. Ferguson ,  Daniel Y. Chung ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

IPC分类号： G04F800

CPC分类号： G01R31/3016 ,  G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/31725 ,  G01R31/318516

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 相位鉴别器对振荡器的输出进行采样，并累加表示通过测试电路传播的上升或下降信号转换的信号传播延迟的数据。 然后，与测试电路相关的最差情况延迟可以表示为两者中较长的时间。 了解精确的最坏情况延迟允许IC A设计者将保护带最小化，从而保证更高的速度性能。

公开(公告)号：US06466520B1

公开(公告)日：2002-10-15

申请号：US09244753

申请日：1999-02-05

申请人： Gil A. Speyer ,  David L. Ferguson ,  Daniel Y. Chung ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

发明人： Gil A. Speyer ,  David L. Ferguson ,  Daniel Y. Chung ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

IPC分类号： G04F800

CPC分类号： G01R31/3016 ,  G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/31725 ,  G01R31/318516

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 相位鉴别器对振荡器的输出进行采样，并累加表示通过测试电路传播的上升或下降信号转换的信号传播延迟的数据。 与测试电路相关的最坏情况延迟可以表示为两者中较长的时间。 了解精确的最坏情况延迟允许IC设计者将保护带最小化，从而保证更高的速度性能。

公开(公告)号：US06275191B1

公开(公告)日：2001-08-14

申请号：US09634698

申请日：2000-08-08

申请人： Austin H. Lesea ,  Robert O. Conn

发明人： Austin H. Lesea ,  Robert O. Conn

IPC分类号： H01Q138

CPC分类号： H01Q21/0037 ,  H01Q1/38

摘要： The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit. Antenna/receiver circuit pairs are disposed at various locations across the surface of the integrated circuit where the signal is to be received and used. Other methods and embodiments are disclosed.

公开(公告)号：US6069849A

公开(公告)日：2000-05-30

申请号：US115138

申请日：1998-07-14

申请人： Christopher H. Kingsley ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

发明人： Christopher H. Kingsley ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

IPC分类号： G01R27/04 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  G04F8/00 ,  G01R15/12

CPC分类号： G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。 最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。 相位鉴别器对振荡器的输出采样，并累加表示该信号占空比的数据。 然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

公开(公告)号：US6008666A

公开(公告)日：1999-12-28

申请号：US53875

申请日：1998-04-01

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17736 ,  H03K19/1778

摘要： Described is a user-controlled, variable-delay interconnect structure for a programmable logic device (PLD), and a method for using this structure. In accordance with the invention, the signal propagation delays for selected signal paths can be precisely adjusted either while the PLD is being programmed or while the PLD is operating as a logic device. The delays are adjusted by selectively connecting otherwise unused interconnect lines to the signal path to increase the capacitive load on the interconnect lines that define the signal path. The ability to control the load on selected signal paths advantageously enables a user to precisely match the signal propagation delays of two or more signal paths. In one embodiment, the loads of selected signal paths can be modified while the FPGA is operational.

摘要翻译： 描述了用于可编程逻辑器件（PLD）的用户控制的可变延迟互连结构以及使用该结构的方法。 根据本发明，当PLD被编程或者当PLD作为逻辑器件操作时，可以精确地调整所选信号路径的信号传播延迟。 通过选择性地连接未使用的互连线到信号路径来调整延迟，以增加限定信号路径的互连线上的容性负载。 控制所选信号路径上的负载的能力有利地使用户能够精确地匹配两个或更多个信号路径的信号传播延迟。 在一个实施例中，可以在FPGA运行时修改所选择的信号路径的负载。