公开(公告)号：US20090206442A1

公开(公告)日：2009-08-20

申请号：US12033322

申请日：2008-02-19

申请人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

发明人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76232

摘要： A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

摘要翻译： 一种形成用于半导体器件的浅沟槽隔离（STI）区域的方法，所述方法包括在半导体衬底内限定STI沟槽开口; 用初始沟槽填充材料填充STI沟槽开口; 在对应于STI沟槽开口的位置处限定衬底上的纳米尺度开口的图案; 将纳米级开口的图案转移到沟槽填充材料中，以便在沟槽填充材料中限定多个垂直取向的纳米级开口; 并用另外的沟槽填充材料堵塞纳米级开口的上部，从而在衬底中限定多孔STI区域。

公开(公告)号：US07541065B2

公开(公告)日：2009-06-02

申请号：US11820302

申请日：2007-06-18

申请人： Colin J. Brodsky ,  Wai-Kin Li ,  Steven A. Scheer

发明人： Colin J. Brodsky ,  Wai-Kin Li ,  Steven A. Scheer

IPC分类号： B05D7/00

CPC分类号： B32B27/00 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/265 ,  Y10T428/31504 ,  Y10T428/3154 ,  Y10T428/31544 ,  Y10T428/31855

摘要： A method is provided for forming a film stack in which a first film including a first polymer is formed on a substrate. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface disposed on the first film. The second film can have a thickness at which a free energy of the second film would be negative if the second film were disposed directly on the substrate. Desirably, the resulting second film is substantially free of dewetting defects.

摘要翻译： 提供了一种用于形成膜叠层的方法，其中在基板上形成包括第一聚合物的第一膜。 可以包括第一聚合物以外的第二聚合物的第二膜形成为具有设置在第一膜上的内表面。 如果第二膜直接设置在基板上，则第二膜可以具有第二膜的自由能为负的厚度。 理想地，所得到的第二膜基本上没有脱湿缺陷。

公开(公告)号：US20090072410A1

公开(公告)日：2009-03-19

申请号：US12256735

申请日：2008-10-23

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

公开(公告)号：US20090035588A1

公开(公告)日：2009-02-05

申请号：US11831005

申请日：2007-07-31

申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

IPC分类号： B32B15/04 ,  H01L21/44

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

公开(公告)号：US20090026574A1

公开(公告)日：2009-01-29

申请号：US11828718

申请日：2007-07-26

申请人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

发明人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/49107 ,  H01L2924/00

摘要： An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

摘要翻译： 在半导体衬底上形成电熔丝和第一电介质层。 含有两个或更多个不同聚合物嵌段组分的自组装嵌段共聚物被施加到由电介质模板层包围的凹陷区域中。 然后将自组装嵌段共聚物退火以形成具有亚光刻直径的多个圆的图案。 通过反应离子蚀刻将多个圆圈的图案转移到第一介电层中，其中，在熔体上方的第一介电层的部分具有包括多个圆柱形孔的蜂窝图案。 通过非共形化学气相沉积在圆柱形孔上方形成第二介电层，并在融合体上形成亚光刻腔。 亚光刻腔相对于介质材料提供与熔丝相关的增强的热绝缘，使得电熔丝可以用较少的编程电流编程。

公开(公告)号：US07439172B2

公开(公告)日：2008-10-21

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US20080203589A1

公开(公告)日：2008-08-28

申请号：US11678163

申请日：2007-02-23

申请人： Todd C. Bailey ,  Ryan P. Deschner ,  Wai-Kin Li ,  Roger A. Quon

发明人： Todd C. Bailey ,  Ryan P. Deschner ,  Wai-Kin Li ,  Roger A. Quon

IPC分类号： H01L23/544

CPC分类号： G06F17/5068 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached.

摘要翻译： 一种在半导体晶片上设计特征的方法。 提供了由晶片上的切口区域分开的小芯片的主动或功能特征的设计。 该方法然后包括确定小灯特征的图案密度，以及在未被活动或功能特征覆盖的小区区域以及在切口区域中应用间隔的虚拟特征图案。 虚拟特征被均匀地扩大或缩小，直到达到所需的虚拟特征图案密度。

公开(公告)号：US20080171432A1

公开(公告)日：2008-07-17

申请号：US11623478

申请日：2007-01-16

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一电介质层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US20080132070A1

公开(公告)日：2008-06-05

申请号：US11566848

申请日：2006-12-05

申请人： Wai-Kin Li ,  Haining Yang

发明人： Wai-Kin Li ,  Haining Yang

IPC分类号： H01L21/44

CPC分类号： H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

摘要： Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

摘要翻译： 通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。 然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。 退火步骤将多晶硅转化为硅化物。 由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。 使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

公开(公告)号：US20080099845A1

公开(公告)日：2008-05-01

申请号：US11552641

申请日：2006-10-25

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/8238

CPC分类号： H01L21/28123 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L29/66583 ,  H01L29/78

摘要： A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个晶体管的半导体结构，其中所述至少一个晶体管具有亚光刻沟道长度。 还提供了使用可以使用预制的硬掩模图案放置在特定位置的自组装嵌段共聚物来形成这种半导体结构的方法。