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公开(公告)号：US08782432B2
公开(公告)日：2014-07-15
申请号：US13524000
申请日：2012-06-15
申请人： Daisuke Oshida , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota , Shigeru Furuta
发明人： Daisuke Oshida , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota , Shigeru Furuta
CPC分类号： G06F21/78 , G06F12/1408 , G06F21/72 , G06F21/73 , G06F21/79 , G06F2221/2107 , G06F2221/2129 , G09C1/00 , H04L9/002 , H04L9/0866 , H04L2209/08 , H04L2209/12
摘要： A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.
摘要翻译： 相关技术的半导体装置存在存储的机密信息的安全性不足的问题。 本发明的半导体器件具有唯一的代码，该代码对于器件是唯一的，并且从唯一代码生成唯一代码对应的信息。 半导体器件具有其中通过加密机密信息获得的特定信息被存储在与唯一代码对应信息相关联的区域中的存储区域。 从存储器区域读取的特定信息用唯一的代码对应信息加密以生成机密信息。
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72.发明申请公开(公告)号：US20120324310A1
公开(公告)日：2012-12-20
申请号：US13523969
申请日：2012-06-15
申请人： Daisuke OSHIDA , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota
发明人： Daisuke OSHIDA , Shigeru Furuta , Masayuki Hirokawa , Akira Yamazaki , Takashi Fujimori , Shigemasa Shiota
CPC分类号： H04L9/3226 , H03M13/29 , H03M13/63 , H04L9/3278 , H04L2209/04 , H04L2209/08 , H04L2209/34
摘要： A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.
摘要翻译： 相关技术的半导体器件具有无法充分确保写入数据时的安全性的问题。 本发明的半导体器件具有：唯一代码生成单元，其生成初始唯一代码，其是设备唯一的值，并且包括随机位中的错误; 第一纠错单元，校正所述初始唯一码中的错误以产生中间唯一码; 第二纠错单元，修正中间唯一码中的错误，以产生第一确定唯一码; 以及解密单元，利用所述第一确定唯一代码，通过由外部设备通过基于所述中间特征码产生的密钥信息对机密信息进行加密而获得的传输数据进行解密，以生成机密信息。
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公开(公告)号：US08015428B2
公开(公告)日：2011-09-06
申请号：US12136988
申请日：2008-06-11
IPC分类号： G06F1/04
摘要： A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.
摘要翻译： 处理装置包括与外部时钟同步的数据传送接口及其控制电路，内部振荡器和接口及其控制电路，用于通过内部振荡器产生的内部时钟进行数据传输。 在处理装置中，提供了根据接口在内部时钟和外部时钟之间切换系统时钟的时钟控制电路。 当系统时钟切换时，在CPU设置为休眠状态之后进行切换，在切换完成后，释放CPU的休眠状态以重启动作。
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公开(公告)号：US07752526B2
公开(公告)日：2010-07-06
申请号：US11747937
申请日：2007-05-14
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara , Kinji Mitani
IPC分类号： G11C29/00
CPC分类号： G07F7/084 , G06F11/1044 , G06Q20/341 , G07F7/1008
摘要： The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable. If uncorrectable (there are more correction locations than X locations), the control circuit notifies the information processing device that the user data is uncorrectable, and then transfers the user data and the management data to the information processing device.
摘要翻译： 通过在信息存储设备内进行小数据校正并且在信息处理设备中执行主要错误校正，数据的可靠性显着增加，而不会显着增加成本。 当从信息处理装置发出用于传送用于读取的用户数据的请求时，控制电路将用户数据和管理数据传送到检错用户数据的错误检测电路。 如果用户数据不包含错误，则控制电路通知信息处理装置可以传送用户数据，并将其传送到信息处理装置。 如果用户数据包含错误，X计数错误位置和校正数据计算电路使用用户数据和管理数据来计算校正位置和校正数据，并且判断校正位置是否可校正。 如果不可校正（比X位置更多的校正位置），则控制电路向信息处理设备通知用户数据是不可校正的，然后将用户数据和管理数据传送到信息处理设备。
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公开(公告)号：US07596041B2
公开(公告)日：2009-09-29
申请号：US11905683
申请日：2007-10-03
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
IPC分类号： G11C7/00
CPC分类号： G06F13/385 , G11C5/14 , G11C7/24
摘要： The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.
摘要翻译： 本发明旨在通过在数据传送过程中即使基于紧急停止请求来确保数据的保护来大大提高可靠性。 本发明提供一种采用存储卡等形式的数据存储系统。 在读/写数据传送处理期间，当从主机的信息处理器接收到请求紧急停止的紧急停止信号时，控制电路立即停止传送处理，并向信息处理器通知读取的数据传送结束。 此时，无论传输是正常还是异常地完成，都会通知读取数据传输的结束。 即使当在通知信息处理器之后再次从信息处理器接收到读取数据传送的结束而不传送数据时，控制器向信息处理器通知读取数据的不可转移的状态。
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公开(公告)号：US07552311B2
公开(公告)日：2009-06-23
申请号：US11711084
申请日：2007-02-27
申请人： Fumio Hara , Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya
发明人： Fumio Hara , Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0866 , G06F2212/2146 , G06F2212/6022
摘要： The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.
摘要翻译： 本发明提供一种可以灵活地决定要被预读的数据的存储装置。 根据本发明的存储装置包括：非易失性存储器; 具有比非易失性存储器更高的访问速度的缓冲存储器; 和控制电路。 控制电路创建一个预读数据管理表，其将从外部输入的预读命令指定的预读数据的逻辑地址与用于存储预读数据的缓冲存储器地址相关联。 此外，控制电路从非易失性存储器读取由该命令指定的数据，并将其作为预读数据存储在缓冲存储器中。 当从外部输入的读取命令中指定的逻辑地址与由预读数据管理表相关联的逻辑地址匹配时，控制电路从缓冲存储器输出对应的预读数据。
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公开(公告)号：US07475165B2
公开(公告)日：2009-01-06
申请号：US11058254
申请日：2005-02-16
申请人： Kinji Mitani , Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
发明人： Kinji Mitani , Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
IPC分类号： G06F13/10
摘要： Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.
摘要翻译： 通过使用相同的控制器来支持外部模拟模块和内部模拟模块，显着减少了半导体数据存储装置的生产成本。 在数据处理系统中，控制器具有由保险丝组成的开关元件。 在由外部电源电路，外部电源监视器电路和时钟发生器元件组成的外部模拟模块之间切换，以及内部电源电路，内部电源监视电路， 激励振荡器电路通过任意断开保险丝来执行。 例如，当将由外部电源监视电路产生的内部电源电压Vdd1提供给控制器等时，熔丝断开。 因此，当使用交错操作时，可以通过例如选择外部模拟模块来根据目的采取措施。
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公开(公告)号：US20080137452A1
公开(公告)日：2008-06-12
申请号：US11905683
申请日：2007-10-03
申请人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
发明人： Shigemasa Shiota , Hiroyuki Goto , Hirofumi Shibuya , Fumio Hara
IPC分类号： G11C7/00
CPC分类号： G06F13/385 , G11C5/14 , G11C7/24
摘要： The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.
摘要翻译： 本发明旨在通过在数据传送过程中即使基于紧急停止请求来确保数据的保护来大大提高可靠性。 本发明提供一种采用存储卡等形式的数据存储系统。 在读/写数据传送处理期间，当从主机的信息处理器接收到请求紧急停止的紧急停止信号时，控制电路立即停止传送处理，并向信息处理器通知读取的数据传送结束。 此时，无论传输是正常还是异常地完成，都会通知读取数据传输的结束。 即使当在通知信息处理器之后再次从信息处理器接收到读取数据传送的结束而不传送数据时，控制器向信息处理器通知读取数据的不可转移的状态。
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公开(公告)号：US20070174573A1
公开(公告)日：2007-07-26
申请号：US11723735
申请日：2007-03-21
CPC分类号： G06F21/79 , G06F12/1425
摘要： To prevent stored information from being changed even at the occurrence of an abnormal condition in an upstream side of a system due to uncontrollable run of an OS. A nonvolatile storage means having data storage areas and management areas for them in units of predetermined physical addresses has an access protect definition table TLB in a predetermined physical address, and the table has access attribute information defining whether to permit or not access to the data storage areas in association with the physical addresses. The memory system itself possesses access attribute information defining whether to permit or not a write to and a read from the data storage areas in association with addresses to implement an access protect function for write and read. Therefore, the access protect function is maintained even if an abnormal condition occurs in a host device that manages the memory system or controls it as a peripheral circuit.
摘要翻译： 为了防止由于OS的不可控的运行而导致在系统的上游侧发生异常状况时存储的信息被改变。 以预定物理地址为单位具有数据存储区域和管理区域的非易失性存储装置具有预定物理地址中的访问保护定义表TLB，并且该表具有定义是否允许或不访问数据存储的访问属性信息 与物理地址相关的区域。 存储器系统本身具有定义是否允许与地址相关联的数据存储区域的写入和读取的访问属性信息，以实现用于写入和读取的访问保护功能。 因此，即使在管理存储器系统的主机设备中发生异常情况或将其控制为外围电路，也保持访问保护功能。
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公开(公告)号：US20070147150A1
公开(公告)日：2007-06-28
申请号：US11711085
申请日：2007-02-27
申请人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
发明人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G11C29/00
CPC分类号： G06F11/1666 , G06F11/004 , G06F11/20 , G06F11/2053 , G11C16/04 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , G11C2229/723
摘要： It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.
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