公开(公告)号：US20050071544A1

公开(公告)日：2005-03-31

申请号：US10673801

申请日：2003-09-29

申请人： Louis Hsu ,  Brian Ji ,  Li-Kong Wang

发明人： Louis Hsu ,  Brian Ji ,  Li-Kong Wang

IPC分类号： G06F12/00 ,  G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.

摘要翻译： 内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线 ，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。

公开(公告)号：US06603683B2

公开(公告)日：2003-08-05

申请号：US09888774

申请日：2001-06-25

申请人： Louis Hsu ,  Li-Kong Wang

发明人： Louis Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/12 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/4076

摘要： A decoding scheme for simultaneously executing multiple operations for a stacked-bank type semiconductor memory device is disclosed. A decoding unit is provided to a memory bank group comprising a plurality of memory banks. When read and write bank addresses match with two different memory banks within the same memory bank group, the decoding unit receives the read and write addresses and generates two different row selection signals for the read and write operations in two different banks. Based on the row selection signals, the row decoder unit in the two matching banks simultaneously activates a target row designated by the read/write addresses.

公开(公告)号：US06529402B1

公开(公告)日：2003-03-04

申请号：US10094533

申请日：2002-03-08

申请人： John E. Andersen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： John E. Andersen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C1100

CPC分类号： G11C11/417 ,  G11C5/025 ,  G11C8/08

摘要： A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.

摘要翻译： 堆叠块阵列架构，用于低功耗应用的SRAM存储器。 该架构仅打开所需的数据单元和感测电路以访问感兴趣的特定数据单元组。 通过使用更短和更宽的字线大小减小字线延迟。 虽然功耗较低，但通过减少字线和位线的负载来提高性能。

公开(公告)号：US20050180521A1

公开(公告)日：2005-08-18

申请号：US10708240

申请日：2004-02-18

申请人： Louis Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： H04L1/22 ,  H04L25/02 ,  H04L25/08 ,  H04L27/04

CPC分类号： H04L1/22 ,  H04L25/029 ,  H04L25/08

摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

公开(公告)号：US06603690B1

公开(公告)日：2003-08-05

申请号：US10091663

申请日：2002-03-06

申请人： Howard Hao Chen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Howard Hao Chen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C29/802

摘要： A static column redundancy scheme for a semiconductor memory such as an eDRAM. By utilizing the existing scan registers for SRAM array testing, the column redundancy information of each bank or each microcell of the memory chip can be scanned, stored and programmed during the power-on period. Two programming methods are disclosed to find the column redundancy information on the fly. In the first method, the column redundancy information is first stored in the SRAM, and is then written into the program registers of the corresponding bank or microcell location. In the second method, the column redundancy information is loaded directly into the program registers of a bank or microcell location according to the bank address information without loading the SRAM. Since the new static column redundancy scheme does not need to compare the incoming addresses, it eliminates the use of control and decoding circuits, which significantly reduces the power consumption for memory macros.

摘要翻译： 用于诸如eDRAM的半导体存储器的静态列冗余方案。 通过利用现有的扫描寄存器进行SRAM阵列测试，可以在上电期间扫描，存储和编程存储器芯片的每个存储体或每个微单元的列冗余信息。 公开了两种编程方法来即时查找列冗余信息。 在第一种方法中，列冗余信息首先存储在SRAM中，然后被写入对应的存储体或微小区位置的程序寄存器中。 在第二种方法中，列冗余信息根据存储体地址信息被直接加载到存储体或微小区位置的程序寄存器中而不加载SRAM。 由于新的静态列冗余方案不需要比较输入地址，因此无需使用控制和解码电路，这显着降低了存储宏的功耗。

公开(公告)号：US06504173B2

公开(公告)日：2003-01-07

申请号：US09757153

申请日：2001-01-09

申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： H01L3300

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.

摘要翻译： 本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。 该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。 还公开了利用本发明的方法制造的双栅结构。

公开(公告)号：US06356134B1

公开(公告)日：2002-03-12

申请号：US09531734

申请日：2000-03-21

申请人： Lawrence A. Clevenger ,  Louis L. C. Hsu ,  Li-Kong Wang ,  Kevin P. Guay

发明人： Lawrence A. Clevenger ,  Louis L. C. Hsu ,  Li-Kong Wang ,  Kevin P. Guay

IPC分类号： G06F104

CPC分类号： H03K3/0315 ,  G06F1/08 ,  H03K3/354

摘要： A universal clock generator circuit, in accordance with the present invention, includes an oscillator unit including circuitry for providing a first clock frequency. A plurality of load blocks are included. The load blocks are selectively connectable to the oscillator such that a range of clock rates are derived from the first clock frequency by selectively connecting a number of the load blocks to the oscillator unit to provide one of a plurality of clock frequencies from a same output.

摘要翻译： 根据本发明的通用时钟发生器电路包括包括用于提供第一时钟频率的电路的振荡器单元。 包括多个加载块。 负载块可选择性地连接到振荡器，使得通过选择性地将多个负载块连接到振荡器单元从相同的输出提供多个时钟频率中的一个，从第一时钟频率导出一定范围的时钟速率。

公开(公告)号：US06207530B1

公开(公告)日：2001-03-27

申请号：US09100900

申请日：1998-06-19

申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： H01L2176

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.

摘要翻译： 本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。 该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。 还公开了利用本发明的方法制造的双栅结构。

公开(公告)号：US20060270098A1

公开(公告)日：2006-11-30

申请号：US11499364

申请日：2006-08-04

申请人： Lawrence Clevenger ,  Louis Hsu ,  Carl Radens ,  Li-Kong Wang ,  Kwong Wong

发明人： Lawrence Clevenger ,  Louis Hsu ,  Carl Radens ,  Li-Kong Wang ,  Kwong Wong

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/30

CPC分类号： H01C7/005 ,  H01C7/006 ,  H01C17/075 ,  H01G4/18 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5328 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

公开(公告)号：US20050043910A1

公开(公告)日：2005-02-24

申请号：US10643549

申请日：2003-08-19

申请人： Daniel Knebel ,  William Reohr ,  Li-Kong Wang

发明人： Daniel Knebel ,  William Reohr ,  Li-Kong Wang

IPC分类号： G06F1/04 ,  G06F11/00 ,  G06F19/00

CPC分类号： G06F11/008

摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。