公开(公告)号：US20050043910A1

公开(公告)日：2005-02-24

申请号：US10643549

申请日：2003-08-19

申请人： Daniel Knebel ,  William Reohr ,  Li-Kong Wang

发明人： Daniel Knebel ,  William Reohr ,  Li-Kong Wang

IPC分类号： G06F1/04 ,  G06F11/00 ,  G06F19/00

CPC分类号： G06F11/008

摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。

公开(公告)号：US20050094445A1

公开(公告)日：2005-05-05

申请号：US10976598

申请日：2004-10-29

申请人： Yu Lu ,  William Reohr ,  Roy Scheuerlein

发明人： Yu Lu ,  William Reohr ,  Roy Scheuerlein

IPC分类号： G11C7/00 ,  G11C11/15 ,  G11C11/16

CPC分类号： G11C11/16

摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

摘要翻译： 磁性随机存取存储器电路包括多个磁存储器单元，每个存储单元包括具有容易轴的磁存储元件和与其相关联的硬轴，以及多个列线和行线，用于选择性地访问一个或多个 的存储单元，每个存储器单元靠近一列列线和一行行的交点。 每个磁存储单元被布置成使得容易轴基本上平行于感测电流的流动方向，并且硬轴基本上平行于写入电流的流动方向。

公开(公告)号：US20070159902A1

公开(公告)日：2007-07-12

申请号：US11330539

申请日：2006-01-12

申请人： William Reohr

发明人： William Reohr

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to selectively drive the pair of complementary bit lines to a first voltage in response to a first control signal. The latch circuit is adapted for connection to the pair of complementary bit lines. The sense amplifier circuit further includes a replication circuit adapted for connection to the pair of complementary bit lines. The replication circuit is operative to selectively transfer a voltage representative of a logic state on a first bit line of the pair of complementary bit lines to a second bit line of the pair of complementary bit lines in response to at least a second control signal.

公开(公告)号：US20070223298A1

公开(公告)日：2007-09-27

申请号：US11754422

申请日：2007-05-29

申请人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

发明人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

公开(公告)号：US20050108480A1

公开(公告)日：2005-05-19

申请号：US10714105

申请日：2003-11-14

申请人： Anthony Correale ,  James Dieffenderfer ,  Robert Goldiez ,  Thomas Speier ,  William Reohr

发明人： Anthony Correale ,  James Dieffenderfer ,  Robert Goldiez ,  Thomas Speier ,  William Reohr

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

摘要： A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data stored in each of the ways. A translation device determines from a system address a tag identifying one of the ways. A first comparator compares tags in the address with a tag stored in the first tag memory. A second comparator compares a tag in the address with a tag stored in the second tag memory. A clock signal supplies clock signals to one or both of the ways in response to an access mode signal. The system can be operated so that either both ways of the associative data cache are clocked, in a high speed access mode, or it can apply clock signals to only one of the ways selected by an output from the first and second comparators in a power efficient mode of operation.

摘要翻译： 一种用于访问具有至少两种在相同地址处存储数据的方式的数据高速缓存的系统和方法。 第一和第二标签存储器存储识别以每种方式存储的数据的第一和第二组标签。 翻译装置从系统地址确定识别方式之一的标签。 第一个比较器将地址中的标签与存储在第一标签存储器中的标签进行比较。 第二比较器将地址中的标签与存储在第二标签存储器中的标签进行比较。 响应于访问模式信号，时钟信号将时钟信号提供给一种或两种方式。 可以对系统进行操作，使得关联数据高速缓存的两种方式都以高速访问模式被计时，或者它可以将时钟信号仅以来自第一和第二比较器的输出的功率中的一种方式应用于时钟信号 高效的运行模式。

公开(公告)号：US20050102475A1

公开(公告)日：2005-05-12

申请号：US10704452

申请日：2003-11-07

申请人： William Reohr ,  Zhigang Hu

发明人： William Reohr ,  Zhigang Hu

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862

摘要： A system and method for reducing latency in memory systems is provided. A copy way is established in a set of a set associative cache, which is physically closer to a requesting entity than other memory positions. Likely to be accessed data is copied to the copy way for subsequent access. In this way, subsequent accesses of the most likely data have their access time reduced due to the physical proximity of the data being close to the requesting entity. Methods herein further provide ranking and rearranging blocks in the cache based on coupled local and global least recently used (LRU) algorithms to reduce latency time.

摘要翻译： 提供了用于减少存储器系统中的延迟的系统和方法。 在一组集合的关联高速缓存中建立复制方式，其在物理上更接近请求实体而不是其他存储器位置。 可能被访问的数据被复制到复制方式以供后续访问。 以这种方式，由于接近请求实体的数据的物理接近度，对最可能的数据的后续访问具有其访问时间的减少。 本文中的方法还基于耦合的本地和全局最近最少使用的（LRU）算法来提供高速缓存中的排序和重排块，以减少等待时间。

公开(公告)号：US20070183238A1

公开(公告)日：2007-08-09

申请号：US11697036

申请日：2007-04-05

申请人： William Reohr

发明人： William Reohr

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to selectively drive the pair of complementary bit lines to a first voltage in response to a first control signal. The latch circuit is adapted for connection to the pair of complementary bit lines. The sense amplifier circuit further includes a replication circuit adapted for connection to the pair of complementary bit lines. The replication circuit is operative to selectively transfer a voltage representative of a logic state on a first bit line of the pair of complementary bit lines to a second bit line of the pair of complementary bit lines in response to at least a second control signal.

摘要翻译： 用于感测存储器电路中所选存储单元的逻辑状态的读出放大器电路包括预充电电路和锁存电路。 预充电电路适于连接到对应于所选择的存储器单元的一对互补位线，并且可操作以响应于第一控制信号选择性地将该对互补位线驱动到第一电压。 锁存电路适于连接到该对互补位线。 读出放大器电路还包括适于连接到该对互补位线的复制电路。 复制电路可操作以响应于至少第二控制信号，将表示该对互补位线的第一位线上的逻辑状态的电压选择性地传送到该对互补位线对的第二位线。

公开(公告)号：US20070025170A1

公开(公告)日：2007-02-01

申请号：US11190542

申请日：2005-07-27

申请人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

发明人： John Barth ,  Paul Parries ,  William Reohr ,  Matthew Wordeman

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

公开(公告)号：US20060107090A1

公开(公告)日：2006-05-18

申请号：US10977432

申请日：2004-10-29

申请人： Philip Emma ,  Robert Montoye ,  William Reohr

发明人： Philip Emma ,  Robert Montoye ,  William Reohr

IPC分类号： G06F11/00

CPC分类号： G06F12/0893 ,  G06F11/1064 ,  G06F2212/1056 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/4096 ,  G11C2029/0411 ,  G11C2207/2245 ,  G11C2211/4062 ,  Y02D10/13

摘要： Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.

摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括错误编码电路，其操作以接收输入数据字并产生存储在动态存储器中的编码数据字。 该装置还包括一个解码电路，用于从动态存储器接收编码的数据字，以检测从动态存储器读取的输入数据字中的至少一个或多个单向错误，并且当至少一个错误 检测出指示输入数据字包含过期数据的错误信号。 包括在装置中的控制电路被配置为响应于该误差信号启动一个或多个动作。

公开(公告)号：US20060041720A1

公开(公告)日：2006-02-23

申请号：US10920844

申请日：2004-08-18

申请人： Zhigang Hu ,  William Reohr

发明人： Zhigang Hu ,  William Reohr

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0864 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/271

摘要： A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.

摘要翻译： 公开了一种用于替换具有非均匀集合关联高速缓冲存储器的计算机系统中的高速缓存行的方法。 该方法将访问延迟作为替代线路的现有排名指南的附加因素，该行的排名越高，越可能从缓存中逐出。 在缓存集中的一组最高排名的高速缓存行中，选择要替换的高速缓存行是为请求实体（例如处理器）提供最低延迟访问的高速缓存行。 将请求实体与存储高速缓存行存储的内存分区分开的距离最大程度上影响访问延迟。