公开(公告)号：US20060270098A1

公开(公告)日：2006-11-30

申请号：US11499364

申请日：2006-08-04

申请人： Lawrence Clevenger ,  Louis Hsu ,  Carl Radens ,  Li-Kong Wang ,  Kwong Wong

发明人： Lawrence Clevenger ,  Louis Hsu ,  Carl Radens ,  Li-Kong Wang ,  Kwong Wong

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/30

CPC分类号： H01C7/005 ,  H01C7/006 ,  H01C17/075 ,  H01G4/18 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5328 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

公开(公告)号：US06777286B2

公开(公告)日：2004-08-17

申请号：US10616243

申请日：2003-07-08

申请人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

发明人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

摘要翻译： 描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供 衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。 本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

公开(公告)号：US20050180521A1

公开(公告)日：2005-08-18

申请号：US10708240

申请日：2004-02-18

申请人： Louis Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： H04L1/22 ,  H04L25/02 ,  H04L25/08 ,  H04L27/04

CPC分类号： H04L1/22 ,  H04L25/029 ,  H04L25/08

摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

公开(公告)号：US06624526B2

公开(公告)日：2003-09-23

申请号：US09872325

申请日：2001-06-01

申请人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

发明人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

摘要翻译： 描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供 衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。 本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

公开(公告)号：US07447273B2

公开(公告)日：2008-11-04

申请号：US10708240

申请日：2004-02-18

申请人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： H01L21/82 ,  H01P1/10

CPC分类号： H04L1/22 ,  H04L25/029 ,  H04L25/08

摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

公开(公告)号：US06556477B2

公开(公告)日：2003-04-29

申请号：US09861788

申请日：2001-05-21

申请人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： G11C1134

CPC分类号： H01L27/105 ,  G11C11/005 ,  H01L27/1052

摘要： A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.

摘要翻译： 提出了在一个衬底上制造的半导体存储器系统，其包括SRAM器件，DRAM器件和闪存器件。 在一个实施例中，SRAM器件是高电阻负载SRAM器件。 在另一个实施例中，DRAM器件是深沟槽DRAM器件。 还提出了一种用于在具有SRAM器件，DRAM器件和闪存器件的一个衬底上制造存储器系统的方法。

公开(公告)号：US20050282323A1

公开(公告)日：2005-12-22

申请号：US11202834

申请日：2005-08-12

申请人： Louis Hsu ,  Li-Kong Wang

发明人： Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L21/20 ,  H01L27/12 ,  D06N7/04 ,  G11B5/64 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/12 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02527 ,  Y10T428/12674 ,  Y10T428/24355 ,  Y10T428/24802 ,  Y10T428/24942 ,  Y10T428/30

摘要： A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.

摘要翻译： 提出了混合基板，即由不同材料制造的基板及其制造方法。 混合基板被配置为在其上制造两个以上的不同器件，具有高导热性，并且被配置用于在其上构图互连以互连在混合基板上制造的不同器件。

公开(公告)号：US20050071544A1

公开(公告)日：2005-03-31

申请号：US10673801

申请日：2003-09-29

申请人： Louis Hsu ,  Brian Ji ,  Li-Kong Wang

发明人： Louis Hsu ,  Brian Ji ,  Li-Kong Wang

IPC分类号： G06F12/00 ,  G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.

摘要翻译： 内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线 ，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。

公开(公告)号：US06603683B2

公开(公告)日：2003-08-05

申请号：US09888774

申请日：2001-06-25

申请人： Louis Hsu ,  Li-Kong Wang

发明人： Louis Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/12 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/4076

摘要： A decoding scheme for simultaneously executing multiple operations for a stacked-bank type semiconductor memory device is disclosed. A decoding unit is provided to a memory bank group comprising a plurality of memory banks. When read and write bank addresses match with two different memory banks within the same memory bank group, the decoding unit receives the read and write addresses and generates two different row selection signals for the read and write operations in two different banks. Based on the row selection signals, the row decoder unit in the two matching banks simultaneously activates a target row designated by the read/write addresses.

公开(公告)号：US06198677B1

公开(公告)日：2001-03-06

申请号：US09221629

申请日：1998-12-29

申请人： Louis Hsu ,  Li-Kong Wang

发明人： Louis Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C7/06

摘要： A new noise control circuit which connects the sense ground node to ground in two specific period of times so that the NSA bouncing is minimized. Preferably these two periods are at the beginning of setting the n-type latch and when the data is transferring and CSL is switching. A pulse of NSET and together with whole CSLEN signal are used to activate the noise control circuit. The noise control circuit can also include a n-FET diode with its gate connected to the source and its drain tied to the Vbleq power supply. It is more preferable to use a low threshold voltage of n-FET device with Vt at 0.55 volts to form the clamp diode.

摘要翻译： 一种新的噪声控制电路，其在两个特定时间段内将感测接地节点连接到地面，使得NSA弹跳最小化。 优选地，这两个周期在设置n型锁存器的开始处以及当数据正在传送和CSL正在切换时。 使用NSET的脉冲和整个CSLEN信号来激活噪声控制电路。 噪声控制电路还可以包括n-FET二极管，其栅极连接到源极，其漏极连接到Vbleq电源。 更优选使用0.5V的Vt的n-FET器件的低阈值电压来形成钳位二极管。