公开(公告)号：US20060270098A1

公开(公告)日：2006-11-30

申请号：US11499364

申请日：2006-08-04

申请人： Lawrence Clevenger ,  Louis Hsu ,  Carl Radens ,  Li-Kong Wang ,  Kwong Wong

发明人： Lawrence Clevenger ,  Louis Hsu ,  Carl Radens ,  Li-Kong Wang ,  Kwong Wong

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/30

CPC分类号： H01C7/005 ,  H01C7/006 ,  H01C17/075 ,  H01G4/18 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5328 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

公开(公告)号：US20060109117A1

公开(公告)日：2006-05-25

申请号：US10904664

申请日：2004-11-22

申请人： Louis Hsu ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang ,  Timothy Dalton

发明人： Louis Hsu ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang ,  Timothy Dalton

IPC分类号： G08B13/14

CPC分类号： G06F21/554 ,  G06F21/81 ,  G06F21/86

摘要： A deactivation management unit for facilitating an intelligent multistage system deactivation process where the deactivation management unit is flexible, facilitates recovery, and renders reverse engineering nearly impossible after the system has been permanently deactivated.

摘要翻译： 一种停用管理单元，用于促进智能多级系统停用过程，其中停用管理单元是灵活的，便于恢复，并且在系统被永久停用之后几乎不可能实现逆向工程。

公开(公告)号：US20060160349A1

公开(公告)日：2006-07-20

申请号：US11034890

申请日：2005-01-14

申请人： Kwong Wong ,  Louis Hsu ,  Timothy Dalton ,  Carl Radens ,  Chih-Chao Yang ,  Lawrence Clevenger ,  Theodorus Standaert

发明人： Kwong Wong ,  Louis Hsu ,  Timothy Dalton ,  Carl Radens ,  Chih-Chao Yang ,  Lawrence Clevenger ,  Theodorus Standaert

IPC分类号： H01L21/4763

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.

摘要翻译： 一种制造互连的方法，包括：在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

公开(公告)号：US20080014663A1

公开(公告)日：2008-01-17

申请号：US11776835

申请日：2007-07-12

申请人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang

发明人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang

IPC分类号： H01L21/00

CPC分类号： H01H59/0009 ,  H01H1/20 ,  H01H2001/0084 ,  H01H2001/0089 ,  Y10T29/49105 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208

摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.

摘要翻译： 描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。 构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 上下电极对; 并且由刚性可移动导电板连接和断开的上下互连布线。 当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。 导电板向上移动，使两条上部互连线路短路。 相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。 由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

公开(公告)号：US20070054489A1

公开(公告)日：2007-03-08

申请号：US11503259

申请日：2006-08-14

申请人： Kwong Wong ,  Louis Hsu ,  Timothy Dalton ,  Carl Radens ,  Chih-Chao Yang ,  Lawrence Clevenger ,  Theodorus Standaert

发明人： Kwong Wong ,  Louis Hsu ,  Timothy Dalton ,  Carl Radens ,  Chih-Chao Yang ,  Lawrence Clevenger ,  Theodorus Standaert

IPC分类号： H01L21/44

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.

摘要翻译： 一种制造互连的方法，包括在电介质材料中提供互连结构，使电介质材料凹陷，使得互连结构的一部分在电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

公开(公告)号：US20060145792A1

公开(公告)日：2006-07-06

申请号：US10905449

申请日：2005-01-05

申请人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang

发明人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang

IPC分类号： H01H51/22

CPC分类号： H01H59/0009 ,  H01H1/20 ,  H01H2001/0084 ,  H01H2001/0089 ,  Y10T29/49105 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208

摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.

摘要翻译： 描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。 构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松动地连接到引导柱; 上下电极对; 以及由可动导电板连接和断开的上下互连布线。 当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。 导电板向上移动，使两条上部互连线路短路。 相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。 由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

公开(公告)号：US20060084256A1

公开(公告)日：2006-04-20

申请号：US10965031

申请日：2004-10-14

申请人： Cyril Cabral ,  Lawrence Clevenger ,  Timothy Dalton ,  Patrick DeHaven ,  Chester Dziobkowski ,  Sunfei Fang ,  Terry Spooner ,  Tsong-Lin Tai ,  Kwong Wong ,  Chin-Chao Yang

发明人： Cyril Cabral ,  Lawrence Clevenger ,  Timothy Dalton ,  Patrick DeHaven ,  Chester Dziobkowski ,  Sunfei Fang ,  Terry Spooner ,  Tsong-Lin Tai ,  Kwong Wong ,  Chin-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888

摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

摘要翻译： 具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。 该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。 优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

公开(公告)号：US20050200024A1

公开(公告)日：2005-09-15

申请号：US11125549

申请日：2005-05-10

申请人： Lawrence Clevenger ,  Stephen Greco ,  Keith Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong Wong

发明人： Lawrence Clevenger ,  Stephen Greco ,  Keith Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong Wong

IPC分类号： H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

摘要翻译： 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

公开(公告)号：US20070128867A1

公开(公告)日：2007-06-07

申请号：US11672363

申请日：2007-02-07

申请人： Anthony Domenicucci ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun Wang ,  Kwong Wong

发明人： Anthony Domenicucci ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun Wang ,  Kwong Wong

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/28518 ,  H01L29/665

摘要： The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.

摘要翻译： 本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。 第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。 第一热循环导致形成含非晶态金属的硅化物。 第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。 在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。 执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。 提供了一种金属硅化物，其厚度是自限制的。

公开(公告)号：US20070087541A1

公开(公告)日：2007-04-19

申请号：US11557259

申请日：2006-11-07

申请人： Kenneth Giewont ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun-Yu Wang ,  Kwong Wong

发明人： Kenneth Giewont ,  Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun-Yu Wang ,  Kwong Wong

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： C23C14/5806 ,  C23C14/16

摘要： Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.

摘要翻译： 公开了一种在硅材料上形成硅化物的方法和结构。 本发明将硅材料置于真空环境中，在硅材料上形成金属，然后在不破坏真空环境的情况下加热硅表面和金属。 当金属沉积时，形成金属和加热硅的工艺可以同时进行而不破坏真空环境以形成硅化物。 在上述处理之后，本发明可以从真空环境中去除硅表面，并对硅表面进行附加加热。 第一加热工艺形成一硅化物，另外的加热形成二硅化物。