公开(公告)号：US12112995B2

公开(公告)日：2024-10-08

申请号：US17839222

申请日：2022-06-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Deepak C. Pandey ,  Haitao Liu ,  Chandra Mouli

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53271 ,  H01L2223/6622

Abstract: Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

公开(公告)号：US12002836B2

公开(公告)日：2024-06-04

申请号：US17154703

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/11

CPC classification number: H01L27/14647 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14689 ,  H01L31/0352 ,  H01L27/14652 ,  H01L31/11

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

公开(公告)号：US11824096B2

公开(公告)日：2023-11-21

申请号：US17468936

申请日：2021-09-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Chandra Mouli

IPC: H01L21/28 ,  H01L21/763 ,  G11C16/04

CPC classification number: H01L29/40114 ,  G11C16/0483 ,  H01L21/763 ,  G11C16/0458

Abstract: Field-effect transistors, and methods of forming such field-effect transistors, including a gate dielectric overlying a semiconductor material, and a control gate overlying the gate dielectric, wherein the control gate includes an instance of a first polycrystalline silicon-containing material consisting essentially of polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material selected from a group consisting of polycrystalline silicon-germanium and polycrystalline silicon-germanium-carbon.

公开(公告)号：US20230171962A1

公开(公告)日：2023-06-01

申请号：US18096341

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L28/00 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11569266B2

公开(公告)日：2023-01-31

申请号：US17308766

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11024643B2

公开(公告)日：2021-06-01

申请号：US16541029

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US10892268B2

公开(公告)日：2021-01-12

申请号：US16421262

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L21/28 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US10418379B2

公开(公告)日：2019-09-17

申请号：US15945215

申请日：2018-04-04

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US10381365B2

公开(公告)日：2019-08-13

申请号：US15677914

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L27/115 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US20190172520A1

公开(公告)日：2019-06-06

申请号：US16250919

申请日：2019-01-17

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Chandra Mouli ,  Haitao Liu

IPC: G11C11/408 ,  G11C8/08 ,  G11C8/14 ,  H01L23/532 ,  H01L23/528 ,  H01L27/108

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.