公开(公告)号：US20180107433A1

公开(公告)日：2018-04-19

申请号：US15841126

申请日：2017-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew A. Prather

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US09921980B2

公开(公告)日：2018-03-20

申请号：US13965008

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0685 ,  G06F3/061 ,  G06F3/0658 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2212/205

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US12197766B2

公开(公告)日：2025-01-14

申请号：US17517107

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather ,  Neal J. Koyle

IPC: G06F11/08 ,  G06F3/06 ,  G06F11/10 ,  G11C29/00

Abstract: Methods for operating a memory system are disclosed herein. In one embodiment, a method comprises receiving first data to be written at a logical address of a memory array, storing the first data at a first physical address corresponding to the logical address, and remapping the logical address to a second physical address, for example, using a soft post package repair operation. The method can further include receiving second data different from the first data to be written at the logical address, storing the second data at the second physical address, and remapping the logical address to the first physical address. In some embodiments, the method can comprise storing first and second ECC data corresponding to the first and second data, respectively. The method can further comprise outputting the first data and/or the second ECC data in response to a read request corresponding to the logical address.

公开(公告)号：US12170127B2

公开(公告)日：2024-12-17

申请号：US18086991

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Brent Keeth ,  Matthew A. Prather

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/04

Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

公开(公告)号：US20240354028A1

公开(公告)日：2024-10-24

申请号：US18625008

申请日：2024-04-02

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Matthew A. Prather

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0673

Abstract: Methods, systems, and devices for metadata communication by a memory device are described. The memory device may receive first data from a first memory die of the memory device and second data from a second memory die of the memory device. The memory device may receive first metadata for the first data from the first memory die and second metadata for the second data from the second memory die. The memory device may combine the first metadata from the first memory die and the second metadata from the second memory die into a set of metadata. And the memory device may transmit the set of metadata to a host device via a pin, such as a metadata pin, allocated for a set of memory dies that includes at least the first memory die and the second memory die.

公开(公告)号：US12067276B2

公开(公告)日：2024-08-20

申请号：US17700187

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F3/06 ,  G03B11/04 ,  G03B17/12 ,  G06F13/16 ,  G06V10/147 ,  G11C5/04 ,  H04N23/51 ,  H04N23/55 ,  G06V20/59

CPC classification number: G06F3/0646 ,  G03B11/045 ,  G03B17/12 ,  G06F3/0659 ,  G06F13/1694 ,  G06V10/147 ,  G11C5/04 ,  H04N23/51 ,  H04N23/55 ,  G06V20/597

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

公开(公告)号：US11960717B2

公开(公告)日：2024-04-16

申请号：US17544629

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0671

Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

公开(公告)号：US11922990B2

公开(公告)日：2024-03-05

申请号：US16838473

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/4074 ,  G06F13/10 ,  G06F1/26 ,  H02M3/156

CPC classification number: G11C11/4074 ,  G06F13/102 ,  G06F1/26 ,  H02M3/156

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

公开(公告)号：US20230342058A9

公开(公告)日：2023-10-26

申请号：US17700187

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G03B11/04 ,  G03B17/12 ,  H04N5/225 ,  G06V10/147

CPC classification number: G03B11/045 ,  G03B17/12 ,  H04N5/2254 ,  H04N5/2252 ,  G06V10/147 ,  G06V20/597

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

公开(公告)号：US11775300B2

公开(公告)日：2023-10-03

申请号：US17960523

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F9/30 ,  G06F3/06 ,  G06F30/331

CPC classification number: G06F9/3004 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/30007 ,  G06F30/331

Abstract: Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.