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公开(公告)号：US20220342810A1
公开(公告)日：2022-10-27
申请号：US17861414
申请日：2022-07-11
IPC分类号： G06F12/02 , G06F12/0882 , G06F12/0873 , G06F11/30 , G06F12/0811
摘要： A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.
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公开(公告)号：US20220291835A1
公开(公告)日：2022-09-15
申请号：US17196694
申请日：2021-03-09
IPC分类号： G06F3/06
摘要： A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.
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公开(公告)号：US11430528B2
公开(公告)日：2022-08-30
申请号：US17001757
申请日：2020-08-25
发明人： Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, Jr. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo′ Righetti
摘要： A change in a read window of a group of memory cells of a memory device that has undergone a plurality of program/erase cycles (PECs) can be determined. read voltage can be determined based at least in part on the determined change in the read window.
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公开(公告)号：US20220269559A1
公开(公告)日：2022-08-25
申请号：US17741940
申请日：2022-05-11
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US20220199170A1
公开(公告)日：2022-06-23
申请号：US17572275
申请日：2022-01-10
摘要： A system can include a memory device and a processing device to perform operations that include detecting a transition associated with the memory device from a first power state to a second power state. Responsive to detecting the transition from the first power state to the second power state, the operations include determining a value of a scan frequency in view of the second power state, wherein one or more scan iterations are initiated in accordance with the value of the scan frequency. The operations further include performing one or more block family calibration operations in accordance with the value of the scan frequency,
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公开(公告)号：US20220189572A1
公开(公告)日：2022-06-16
申请号：US17123993
申请日：2020-12-16
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.
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公开(公告)号：US20220189571A1
公开(公告)日：2022-06-16
申请号：US17122758
申请日：2020-12-15
发明人： Jeffrey S. McNeil, JR. , Karl D. Schuh , Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Kishore K. Muchherla , Gil Golov , Todd A. Marquart , Jiangang Wu , Niccolo' Righetti , Ashutosh Malshe
摘要： Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.
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公开(公告)号：US20220164106A1
公开(公告)日：2022-05-26
申请号：US17100712
申请日：2020-11-20
IPC分类号： G06F3/06
摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.
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公开(公告)号：US20220164105A1
公开(公告)日：2022-05-26
申请号：US17100709
申请日：2020-11-20
IPC分类号： G06F3/06
摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.
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公开(公告)号：US20220155956A1
公开(公告)日：2022-05-19
申请号：US17099546
申请日：2020-11-16
IPC分类号： G06F3/06
摘要： A system can include a memory device and a processing device to perform operations that include identifying voltage offset bins of the memory device, each of the first voltage offset bins satisfying a first age threshold criterion, identifying one or more second voltage offset bins of the memory device, each of the second voltage offset bins satisfying a second age threshold criterion, identifying a first block family associated with one of the first voltage offset bins, and performing a first scan of a first block of the first block family by: identifying, based on determined values of the first data state metric, a first identified voltage offset bin, and identifying one or more values of a second data state metric in scan metadata generated by a second scan, and identifying, based on the one or more values of the second data state metric, a second identified voltage offset bin.
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