公开(公告)号：US12125539B2

公开(公告)日：2024-10-22

申请号：US17861467

申请日：2022-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

IPC: G11C16/10 ,  G06F3/06 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483

Abstract: A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

公开(公告)号：US20240111445A1

公开(公告)日：2024-04-04

申请号：US18526634

申请日：2023-12-01

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/26

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/10 ,  G11C16/26 ,  G11C16/0483

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

公开(公告)号：US11755478B2

公开(公告)日：2023-09-12

申请号：US17667326

申请日：2022-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Mustafa N. Kaynak ,  Shane Nowell

IPC: G06F12/0802 ,  G06F12/06 ,  G11C16/10

CPC classification number: G06F12/0802 ,  G06F12/06 ,  G11C16/107

Abstract: A set of two or more block families associated with a bin boundary of a first voltage bin is identified. A determination of at least a first voltage for a first block family of the plurality of block families and a second voltage for a second block family of the plurality of block families based on values of a data state metric for each of the plurality of block families. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

公开(公告)号：US11733929B2

公开(公告)日：2023-08-22

申请号：US17819857

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steve Kientz

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/0483

Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.

公开(公告)号：US20230153003A1

公开(公告)日：2023-05-18

申请号：US18098439

申请日：2023-01-18

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen ,  Steven Michael Kientz ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G01K3/04 ,  G06F1/324 ,  G06F1/3228

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G01K3/04 ,  G06F1/324 ,  G06F1/3228 ,  G06F3/0679

Abstract: A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

公开(公告)号：US11651828B2

公开(公告)日：2023-05-16

申请号：US17379868

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2216/16

Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A method includes determining that a first programming pass of a programming operation has been performed on a memory cell of the memory component, and performing a dynamic program targeting (DPT) operation on the memory cell to calibrate a first program-verify (PV) target value that results in an adjustment to a placement of a first first-pass programming distribution and a second PV target value that results in an adjustment to a placement of a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

公开(公告)号：US11557357B2

公开(公告)日：2023-01-17

申请号：US17014583

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Larry J. Koudele

IPC: G11C7/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

Abstract: An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.

公开(公告)号：US20220350718A1

公开(公告)日：2022-11-03

申请号：US17868008

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steven S. Williams

IPC: G06F11/30 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  G06F3/06

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device; aggregating temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature; responsive to beginning to program a block residing on the memory device, associating the block with the block family; and in response to the aggregate temperature being greater than or equal to a specified threshold temperature value: performing a soft closure of the block family; initializing an extension timer; continuing to program data to the block; and performing a hard closure of the block family in response to one of the extension timer reaching an extension time value or the block family satisfying a hard closure criteria.

公开(公告)号：US20220300166A1

公开(公告)日：2022-09-22

申请号：US17832842

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Steven Michael Kientz ,  Larry J. Koudele ,  Shane Nowell ,  Michael Sheperek ,  Bruce A. Liikanen

IPC: G06F3/06 ,  G06F11/30

Abstract: A system including a memory device and a processing device, the processing device to identify a first temperature level of a first set of memory blocks associated with the memory device, and a second temperature level of a second set of memory blocks associated with the memory device, and determine that a condition is satisfied based on a comparison of the first temperature level, the second temperature level, and an adjustable threshold level. In response to the condition being satisfied, the processing device is to combine the first set of memory blocks and the second set of memory blocks to generate a combined set of memory blocks.

公开(公告)号：US20220291847A1

公开(公告)日：2022-09-15

申请号：US17826733

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Larry J. Koudele ,  Bruce A. Liikanen

IPC: G06F3/06 ,  G11C29/02 ,  G11C16/34 ,  G11C11/56

Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically adjust the program-verify target according to the feedback measure.