公开(公告)号：US07565633B2

公开(公告)日：2009-07-21

申请号：US11619320

申请日：2007-01-03

申请人： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield

发明人： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy simulated image. Where the lower accuracy simulated image is determined as potentially including an error, a further simulation of the designated portion of the mask layout with a higher accuracy will be performed.

摘要翻译： 公开了一种用于验证光刻工艺的掩模布局的可印刷性的方法，系统和计算机程序产品。 使用精度较低的掩模布局的简化版本来模拟设计的掩模布局的光刻工艺的模拟，以产生较低精度的模拟图像。 在将低精度模拟图像确定为潜在地包括错误的情况下，将执行具有更高精度的掩模布局的指定部分的进一步模拟。

公开(公告)号：US20090125868A1

公开(公告)日：2009-05-14

申请号：US12357648

申请日：2009-01-22

申请人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

发明人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

公开(公告)号：US20090123057A1

公开(公告)日：2009-05-14

申请号：US11937073

申请日：2007-11-08

申请人： Maharaj Mukherjee ,  Ioana Graur ,  Alan E. Rosenbluth

发明人： Maharaj Mukherjee ,  Ioana Graur ,  Alan E. Rosenbluth

IPC分类号： G06K9/00

CPC分类号： G06K9/036 ,  G03F7/70441

摘要： Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of process parameters to said one or more tight clusters; and reporting an error when at least one of said process parameters is away from said one or more tight clusters.

摘要翻译： 本发明的实施例提供了一种执行掩模布局的可印刷性验证的方法。 该方法包括创建一个或多个紧密簇; 计算与所述掩模上的点相关联的一组过程参数; 将所述一组过程参数与所述一个或多个紧密簇进行比较; 并且当至少一个所述过程参数远离所述一个或多个紧密簇时报告错误。

公开(公告)号：US20080247633A1

公开(公告)日：2008-10-09

申请号：US12117934

申请日：2008-05-09

申请人： David L DeMaris ,  Mark A. Lavin ,  William C. Leipold ,  Daniel N. Maynard ,  Maharaj Mukherjee

发明人： David L DeMaris ,  Mark A. Lavin ,  William C. Leipold ,  Daniel N. Maynard ,  Maharaj Mukherjee

IPC分类号： G06K9/00

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A system of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.

摘要翻译： 一种合成布局图案以测试光学邻近校正算法的系统。 该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理​​矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

公开(公告)号：US07415695B2

公开(公告)日：2008-08-19

申请号：US11748575

申请日：2007-05-15

申请人： Bette L. Bergman Reuter ,  David L. DeMaris ,  Mark A. Lavin ,  William C. Leipold ,  Daniel N. Maynard ,  Maharaj Mukherjee

发明人： Bette L. Bergman Reuter ,  David L. DeMaris ,  Mark A. Lavin ,  William C. Leipold ,  Daniel N. Maynard ,  Maharaj Mukherjee

IPC分类号： G06F17/50

CPC分类号： G06T7/001 ,  G06T2207/30148

摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

公开(公告)号：US06996797B1

公开(公告)日：2006-02-07

申请号：US10904600

申请日：2004-11-18

申请人： Lars W. Liebmann ,  James A. Culp ,  Ioana C. Graur ,  Maharaj Mukherjee

发明人： Lars W. Liebmann ,  James A. Culp ,  Ioana C. Graur ,  Maharaj Mukherjee

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

摘要： A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography includes scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image. A first feature of the scaled image is shifted with respect to a second feature thereof in accordance with a predetermined maximum overlay error. An intersection parameter of the first and said second features of the scaled image is calculated so as to determine a yield metric of an ideal layout. A first feature of a simulated wafer image is shifted with respect to a second feature thereof in accordance with the predetermined maximum overlay error. An intersection parameter of the first and said second features of the simulated wafer image is calculated so as to determine a yield metric of a simulated layout, and the yield metric of the simulated wafer image is compared to the yield metric of the scaled image.

摘要翻译： 用于光刻中的分辨率增强技术（RET）和光学邻近校正（OPC）的基于模型的验证的方法包括将绘制的掩模布局的形状缩放到其相应的预期晶片尺寸，以便创建缩放图像。 根据预定的最大重叠误差，缩放图像的第一特征相对于其第二特征偏移。 计算缩放图像的第一和第二特征的交点参数，以便确定理想布局的屈服度量。 模拟晶片图像的第一特征相对于其第二特征根据预定的最大重叠误差而偏移。 计算模拟晶片图像的第一和第二特征的交叉参数，以便确定模拟布局的屈服度量，并将模拟晶片图像的屈服度量与缩放图像的屈服度量进行比较。

公开(公告)号：US20050027829A1

公开(公告)日：2005-02-03

申请号：US10604585

申请日：2003-07-31

申请人： Maharaj Mukherjee

发明人： Maharaj Mukherjee

IPC分类号： G06F20060101 ,  G06F11/00 ,  G06F15/173 ,  G06F15/177

CPC分类号： G06F9/5061 ,  G06F2209/505 ,  H04L67/1002 ,  H04L67/1021 ,  H04L67/1023 ,  H04L67/1034 ,  H04L69/40

摘要： A method is described for configuring a system having a plurality of processors to provide the system with at least one cluster of processors, where each cluster has one service point. A distance is computed from each processor to other processors in the system. A plurality of total distances is then computed, where each total distance is associated with one processor. A minimum total distance is determined from the plurality of total distances. One processor is assigned to be the service point; this processor is the processor having the minimum total distance associated therewith.

摘要翻译： 描述了一种用于配置具有多个处理器的系统以向系统提供至少一个处理器群的方法，其中每个群集具有一个服务点。 从系统中的每个处理器到其他处理器计算距离。 然后计算多个总距离，其中每个总距离与一个处理器相关联。 从多个总距离确定最小总距离。 一个处理器被分配为服务点; 该处理器是具有与其相关联的最小总距离的处理器。

公开(公告)号：US09606542B2

公开(公告)日：2017-03-28

申请号：US13348846

申请日：2012-01-12

申请人： Shang Q. Guo ,  Canturk Isci ,  Jonathan Lenchner ,  Maharaj Mukherjee

发明人： Shang Q. Guo ,  Canturk Isci ,  Jonathan Lenchner ,  Maharaj Mukherjee

IPC分类号： G05D1/02 ,  G08G1/00 ,  G05B19/418

CPC分类号： G05D1/0291 ,  G05B19/41815 ,  G05B2219/39146 ,  G05B2219/39168 ,  G05D1/0274 ,  G05D2201/0207 ,  G08G1/20

摘要： Techniques are provided for discovery and monitoring of an environment using a plurality of robots. A plurality of robots navigate an environment by determining a navigation buffer for each of the robots; and allowing each of the robots to navigate within the environment while maintaining a substantially minimum distance from other robots, wherein the substantially minimum distance corresponds to the navigation buffer, and wherein a size of each of the navigation buffers is reduced over time based on a percentage of the environment that remains to be navigated. The robots can also navigate an environment by obtaining a discretization of the environment to a plurality of discrete regions; and determining a next unvisited discrete region for one of the plurality of robots to explore in the exemplary environment using a breadth-first search. The plurality of discrete regions can be, for example, a plurality of real or virtual tiles.

公开(公告)号：US08719829B2

公开(公告)日：2014-05-06

申请号：US12700414

申请日：2010-02-04

申请人： Maharaj Mukherjee

发明人： Maharaj Mukherjee

IPC分类号： G06F9/46 ,  G06F9/455

CPC分类号： G06F9/52

摘要： Synchronizing processes in a computer system includes creating a predictability model for a process. The predictability model establishes a predicted time slot for a resource that will be needed by the process. The method further requires establishing a predictive request for the resource at the predicted time slot. The predictive request establishes a place holder associated with the process. In addition, the method requires accessing another resource needed by the process for a period of time before the predicted time slot, submitting a request for the resource at the predicted time slot, and processing the request for the process at the resource.

摘要翻译： 计算机系统中的同步过程包括为进程创建可预测性模型。 可预测性模型为进程需要的资源建立预测的时隙。 该方法还需要在预测时隙建立资源的预测请求。 预测要求建立与过程相关联的占位符。 此外，该方法需要在预测时隙之前的一段时间内访问该过程所需的另一资源，在预测时隙提交对资源的请求，并处理该资源处理的请求。

公开(公告)号：US08296702B2

公开(公告)日：2012-10-23

申请号：US12686412

申请日：2010-01-13

申请人： Maharaj Mukherjee

发明人： Maharaj Mukherjee

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for creating a rectilinear non-convex polygonal output representative of a component used to build a VLSI circuit chip from a plurality of points corresponding to a plurality of components of the chip includes: covering the plurality of points with a set of rectangles; creating a Voronoi diagram for the set of rectangles; forming a nearest neighbor tree for the Voronoi diagram; connecting a selected set of the rectangles corresponding to the nearest neighbor tree into a non-convex rectilinear polygon; and applying the non-convex rectilinear polygon to build the VLSI chip.

摘要翻译： 用于创建代表用于从对应于芯片的多个部件的多个点构建VLSI电路芯片的部件的直线非凸多边形输出的方法包括：用一组矩形覆盖多个点; 创建一组矩形的Voronoi图; 形成Voronoi图的最近邻树; 将与最近邻居树相对应的所选择的一组矩形连接到非凸直线多边形中; 并应用非凸直线多边形构建VLSI芯片。