公开(公告)号：US08022467B2

公开(公告)日：2011-09-20

申请号：US12467424

申请日：2009-05-18

申请人： Hirofumi Iikawa ,  Masayuki Tanaka

发明人： Hirofumi Iikawa ,  Masayuki Tanaka

IPC分类号： H01L29/792

CPC分类号： H01L29/42336 ,  H01L21/76224 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2. Each element isolation insulating film includes a high-temperature oxide film formed along lower side surfaces of the charge storage layers between the charge storage layers and a coating type insulating film. The first silicon nitride film is formed on an upper surface of the high-temperature oxide film in upper surfaces of the element isolation insulating films and not on the upper surface of the coating type insulating film.

摘要翻译： 非易失性半导体存储器件包括第一绝缘层，电荷存储层，元件隔离绝缘膜和形成在电荷存储层和元件隔离绝缘膜上的第二绝缘层，并且包括第一氮化硅膜的堆叠结构，第一 氧化硅膜，中间绝缘膜和第二氧化硅膜。 第一氮化硅膜的氮浓度不小于21×10 15原子/ cm 2。 每个元件隔离绝缘膜包括沿电荷存储层和涂层型绝缘膜之间的电荷存储层的下侧表面形成的高温氧化膜。 第一氮化硅膜形成在元件隔离绝缘膜的上表面的高温氧化膜的上表面上，而不是在涂层型绝缘膜的上表面上。

公开(公告)号：US20110203869A1

公开(公告)日：2011-08-25

申请号：US13061638

申请日：2009-09-28

申请人： Masayuki Tanaka ,  Naoaki Oikawa ,  Yuuichi Fukuyama ,  Yuji Takatsuka ,  Takahiro Kuroiwa

发明人： Masayuki Tanaka ,  Naoaki Oikawa ,  Yuuichi Fukuyama ,  Yuji Takatsuka ,  Takahiro Kuroiwa

IPC分类号： B62D5/04

CPC分类号： B62D5/046 ,  B62D5/0481

摘要： In an electric power steering apparatus including capacitor for smoothing out the voltage of battery and relay including a relay contact disposed at a place upstream of the capacitor, a path is provided for directly conducting a terminal voltage of the capacitor from a downstream side of the relay contact to a system power supply supply that generates a source voltage for a control system including controller and the like, so that the system power supply and the control system that is supplied therefrom with electric power for control purpose are utilized as a discharge circuit. Thus is obtained a simplified configuration of circuit responsible for discharging the capacitor.

摘要翻译： 在包括用于平滑电池电压的电容器和包括设置在电容器上游的位置处的继电器触点的继电器触点的电动转向装置中，设置用于从继电器的下游侧直接传导电容器的端子电压的路径 与系统电源接触，产生用于包括控制器等的控制系统的源电压，从而将用于控制的电力供给的系统电源和控制系统用作放电电路。 因此获得了负责放电电容器的电路的简化配置。

公开(公告)号：US20110120849A1

公开(公告)日：2011-05-26

申请号：US12674482

申请日：2008-12-02

申请人： Masaru Morimoto ,  Masayuki Tanaka ,  Katsumi Edo

发明人： Masaru Morimoto ,  Masayuki Tanaka ,  Katsumi Edo

IPC分类号： H01H13/76

CPC分类号： G06F3/0338 ,  G06F3/0362 ,  H01H25/041 ,  H01H2025/043 ,  H01H2025/045 ,  H01H2025/048

摘要： An operation input device includes a base including at least four elastic engagement receiving portions raised at a periphery of a center thereof; a print substrate configured to be stacked and integrated on the base; an annular operation plate mounted on push button switches of the print substrate and configured to prevent slip-out; an operation dial mounted on the annular operation plate on an axial center; and a fixing tool configured to be inserted to a fit-in hole of the operation hole and engage with at least two elastic engagement receiving portions of the base at an edge on a lower side and with an inner peripheral edge of the operation dial.

摘要翻译： 一种操作输入装置，包括：底座，包括在其中心周边隆起的至少四个弹性接合部; 打印基板，被配置为堆叠并集成在所述基座上; 安装在所述打印基板的按钮开关上的环形操作板，用于防止滑出; 操作盘安装在环形操作板上的轴向中心; 以及固定工具，其构造成插入到所述操作孔的嵌合孔中，并且与所述底座的至少两个弹性接合部分在下侧的边缘和所述操作转盘的内周边缘处接合。

公开(公告)号：US20110054172A1

公开(公告)日：2011-03-03

申请号：US12922028

申请日：2009-03-12

申请人： Ryo Iwamura ,  Masayuki Tanaka ,  Tetsushi Katsube ,  Manabu Shigetomi ,  Eiji Okanari ,  Yasunori Tokunaga ,  Hiroshi Fujiwara

发明人： Ryo Iwamura ,  Masayuki Tanaka ,  Tetsushi Katsube ,  Manabu Shigetomi ,  Eiji Okanari ,  Yasunori Tokunaga ,  Hiroshi Fujiwara

IPC分类号： C07D401/14 ,  C07D417/14 ,  C07D401/12 ,  C07D405/14 ,  C07D417/12

CPC分类号： C07D417/14 ,  A61K9/0053 ,  A61K9/2018 ,  A61K9/4858 ,  C07D213/74 ,  C07D401/14 ,  C07D405/14 ,  C07D409/14 ,  C07D417/12

摘要： The present invention provides a novel pyridylaminoacetic acid compound represented by the following formula (1): (wherein R1, R2, R3, Y and Z are as defined in the description and claims), or a pharmacologically acceptable salt thereof. The pyridylaminoacetic acid compound has EP2 agonistic action and is therefore useful as a therapeutic and/or prophylactic agent for respiratory diseases such as asthma or chronic obstructive pulmonary disease.

摘要翻译： 本发明提供由下式（1）表示的新颖的吡啶基氨基乙酸化合物或其药学上可接受的盐，其中R1，R2，R3，Y和Z如说明书和权利要求中所定义。 吡啶基氨基乙酸化合物具有EP2激动作用，因此可用作呼吸系统疾病如哮喘或慢性阻塞性肺疾病的治疗和/或预防剂。

公开(公告)号：US20100308393A1

公开(公告)日：2010-12-09

申请号：US12722111

申请日：2010-03-11

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/40114

摘要： A semiconductor device including a semiconductor substrate having an active region isolated by an element isolation insulating film; a floating gate electrode film formed on a gate insulating film residing on the active region; an interelectrode insulating film formed above an upper surface of the element isolation insulating film and an upper surface and sidewalls of the floating gate electrode film, the interelectrode insulating film being configured by multiple film layers including a high dielectric film having a dielectric constant equal to or greater than a silicon nitride film; a control gate electrode film formed on the interelectrode insulating film; and a silicon oxide film formed between the upper surface of the floating gate electrode film and the interelectrode insulating film; wherein the high dielectric film of the interelectrode insulating film is placed in direct contact with the sidewalls of the floating gate electrode film.

摘要翻译： 一种半导体器件，包括具有通过元件隔离绝缘膜隔离的有源区的半导体衬底; 形成在位于有源区上的栅极绝缘膜上的浮栅电极膜; 在所述元件隔离绝缘膜的上表面上方形成的电极间绝缘膜，以及所述浮栅电极膜的上表面和侧壁，所述电极间绝缘膜由多层膜构成，所述多个膜层包括介电常数等于或等于 大于氮化硅膜; 形成在电极间绝缘膜上的控制栅极电极膜; 以及在所述浮栅电极膜的上表面和所述电极间绝缘膜之间形成的氧化硅膜; 其中，电极间绝缘膜的高电介质膜与浮栅电极膜的侧壁直接接触。

公开(公告)号：US07833856B2

公开(公告)日：2010-11-16

申请号：US11802114

申请日：2007-05-21

申请人： Masayuki Tanaka ,  Hirokazu Ishida

发明人： Masayuki Tanaka ,  Hirokazu Ishida

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.

摘要翻译： 根据本发明的一个方面，提供一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘层，在第一绝缘层上形成为浮栅的第一导电层，形成为第一绝缘层的第二绝缘层 在第一导电层上的电极间绝缘膜，并且包括三层主要包括硅和氧的第一膜，主要包括硅和氮的第二膜和主要包括硅和氧的第三膜，其中硅和氮的组成比 所述第二膜处于所述硅超过化学计量组成的状态，以及在所述第二绝缘膜上形成为控制栅极的第二导电层。

公开(公告)号：US07812391B2

公开(公告)日：2010-10-12

申请号：US12354200

申请日：2009-01-15

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Atsuhiro Suzuki

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Atsuhiro Suzuki

IPC分类号： H01L21/76

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/94

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 Å.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底，具有由以形成在衬底的表面中的预定间隔分开形成的多个沟槽分开形成的多个有源区;形成在衬底的上表面上的第一栅极绝缘膜， 区域，通过依次沉积形成在栅极绝缘膜的上表面上的电荷存储层，第二栅极绝缘膜和控制栅极绝缘膜而形成的存储单元晶体管的栅电极，每个区域中埋设的元件隔离绝缘膜 沟槽，并且由涂覆型氧化物膜形成，并且在半导体衬底和元件隔离绝缘膜之间的边界上形成在每个沟槽内的绝缘膜，所述绝缘膜包含非转移金属原子并且具有不大于5的膜厚度。

公开(公告)号：US07772636B2

公开(公告)日：2010-08-10

申请号：US11785694

申请日：2007-04-19

申请人： Hirokazu Ishida ,  Masayuki Tanaka

发明人： Hirokazu Ishida ,  Masayuki Tanaka

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.

摘要翻译： 非易失性半导体存储器件包括形成在半导体衬底的主表面上的第一电介质层，形成在第一电介质层上的浮栅电极层，通过在浮栅电极层上依次形成下层 主要含有硅和氮的电介质膜，中间电介质膜和主要含有硅和氮的上电介质膜，形成在第二介电层上的控制栅极电极层和通过覆盖第二电介质层中的两个侧表面而形成的掩埋电介质层 包括上述层的层叠结构的栅极宽度方向。 非易失性半导体存储器件还包括在浮置栅极电极层和下部电介质膜之间的界面中形成在掩埋电介质层附近的氧化硅膜。

公开(公告)号：US20100102377A1

公开(公告)日：2010-04-29

申请号：US12467424

申请日：2009-05-18

申请人： Hirofumi IIKAWA ,  Masayuki Tanaka

发明人： Hirofumi IIKAWA ,  Masayuki Tanaka

IPC分类号： H01L29/792 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L29/42336 ,  H01L21/76224 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a plurality of charge storage layers formed on the first insulating layer, a plurality of element isolation insulating films formed between the charge storage layers respectively, a second insulating layer formed on the charge storage layers and the element isolation insulating films, the second insulating layer including a stacked structure of a first silicon nitride film, a first silicon oxide film, an intermediate insulating film having a relative dielectric constant of not less than 7 and a second silicon oxide film, and a control electrode formed on the second insulating layer. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的多个电荷存储层，分别形成在电荷存储层之间的多个元件隔离绝缘膜，第二绝缘层 绝缘层，形成在电荷存储层和元件隔离绝缘膜上，第二绝缘层包括第一氮化硅膜，第一氧化硅膜，相对介电常数不小于7的中间绝缘膜的堆叠结构 和第二氧化硅膜，以及形成在第二绝缘层上的控制电极。 第一氮化硅膜的氮浓度不小于21×10 15原子/ cm 2。

公开(公告)号：USD600655S1

公开(公告)日：2009-09-22

申请号：US29282140

申请日：2007-07-12

申请人： Takeshi Miyasaka ,  Masayuki Tanaka

设计人： Takeshi Miyasaka ,  Masayuki Tanaka