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公开(公告)号：US07714373B2
公开(公告)日：2010-05-11
申请号：US11822437
申请日：2007-07-05
申请人： Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Hirokazu Ishida , Masumi Matsuzaki , Yoshio Ozawa
发明人： Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Hirokazu Ishida , Masumi Matsuzaki , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： There is disclosed a semiconductor device including a plurality of memory cell transistors, each memory cell transistor including a floating gate electrode isolated from each other via an isolation insulating film every memory cell transistor, an inter-electrode insulating film comprising a HfxAl1-xOy film (0.8≦x≦0.95) formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the memory cell transistors are arrayed to form a memory cell array.
摘要翻译： 公开了一种包括多个存储单元晶体管的半导体器件，每个存储单元晶体管包括通过每个存储单元晶体管的隔离绝缘膜彼此隔离的浮栅，包括Hf x Al 1-x O y膜的电极间绝缘膜（ 形成在浮置栅电极上的栅极电极，以及形成在电极间绝缘膜上的控制栅电极，其中存储单元晶体管被排列以形成存储单元阵列。
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公开(公告)号：US20050212036A1
公开(公告)日：2005-09-29
申请号：US11088947
申请日：2005-03-25
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中以限定多个元件形成区域;浮置栅极，通过第一栅极绝缘膜设置在每个元件形成区域上 ，通过第二栅极绝缘膜设置在浮置栅极上的控制栅极和设置在半导体衬底中的源极/漏极区域，其中至少在第二栅极绝缘膜和控制栅极之间的界面处设置相互扩散层。
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公开(公告)号：US20070267682A1
公开(公告)日：2007-11-22
申请号：US11802114
申请日：2007-05-21
申请人： Masayuki Tanaka , Hirokazu Ishida
发明人： Masayuki Tanaka , Hirokazu Ishida
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.
摘要翻译： 根据本发明的一个方面，提供一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘层，在第一绝缘层上形成为浮栅的第一导电层，形成为第一绝缘层的第二绝缘层 在第一导电层上的电极间绝缘膜，并且包括三层主要包括硅和氧的第一膜，主要包括硅和氮的第二膜和主要包括硅和氧的第三膜，其中硅和氮的组成比 所述第二膜处于所述硅超过化学计量组成的状态，以及在所述第二绝缘膜上形成为控制栅极的第二导电层。
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公开(公告)号：US08198159B2
公开(公告)日：2012-06-12
申请号：US12054089
申请日：2008-03-24
IPC分类号： H01L21/324 , H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US20110018048A1
公开(公告)日：2011-01-27
申请号：US12923665
申请日：2010-10-01
申请人： Masayuki Tanaka , Hirokazu Ishida
发明人： Masayuki Tanaka , Hirokazu Ishida
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.
摘要翻译： 根据本发明的一个方面，提供一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘层，在第一绝缘层上形成为浮栅的第一导电层，形成为第一绝缘层的第二绝缘层 在第一导电层上的电极间绝缘膜，并且包括三层主要包括硅和氧的第一膜，主要包括硅和氮的第二膜和主要包括硅和氧的第三膜，其中硅和氮的组成比 所述第二膜处于所述硅超过化学计量组成的状态，以及在所述第二绝缘膜上形成为控制栅极的第二导电层。
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公开(公告)号：US20100255671A1
公开(公告)日：2010-10-07
申请号：US12817675
申请日：2010-06-17
申请人： Hirokazu Ishida , Masayuki Tanaka
发明人： Hirokazu Ishida , Masayuki Tanaka
IPC分类号： H01L21/8247 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.
摘要翻译： 非易失性半导体存储器件包括形成在半导体衬底的主表面上的第一电介质层，形成在第一电介质层上的浮栅电极层，通过在浮栅电极层上依次形成下层 主要含有硅和氮的电介质膜，中间电介质膜和主要含有硅和氮的上电介质膜，形成在第二介电层上的控制栅极电极层和通过覆盖第二电介质层中的两个侧表面而形成的掩埋电介质层 包括上述层的层叠结构的栅极宽度方向。 非易失性半导体存储器件还包括在浮置栅极电极层和下部电介质膜之间的界面中形成在掩埋电介质层附近的氧化硅膜。
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公开(公告)号：US20080311734A1
公开(公告)日：2008-12-18
申请号：US12193531
申请日：2008-08-18
申请人： Masayuki TANAKA , Hirokazu Ishida
发明人： Masayuki TANAKA , Hirokazu Ishida
IPC分类号： H01L21/3205
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.
摘要翻译： 公开了一种具有高介电常数绝缘体的非易失性半导体存储器件及其适用于小型化的制造方法。 根据本发明的一个方面，提供了一种半导体存储装置，包括半导体衬底，通过第一绝缘体在半导体衬底上形成的多个第一导体层，在多个第一导体层之间形成的隔离，硅 形成在第一导体层上的氧化膜，形成在氧化硅膜上的高介电常数绝缘体，并且至少在其与氧化硅膜接触的表面中分离和扩散硅和氧，以及形成的第二导体膜 高介电常数绝缘子上方。
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公开(公告)号：US20080176389A1
公开(公告)日：2008-07-24
申请号：US12054089
申请日：2008-03-24
IPC分类号： H01L21/4763
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US07294878B2
公开(公告)日：2007-11-13
申请号：US11088947
申请日：2005-03-25
IPC分类号： H01L27/108
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中以限定多个元件形成区域;浮置栅极，通过第一栅极绝缘膜设置在每个元件形成区域上 ，通过第二栅极绝缘膜设置在浮置栅极上的控制栅极和设置在半导体衬底中的源极/漏极区域，其中至少在第二栅极绝缘膜和控制栅极之间的界面处设置相互扩散层。
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公开(公告)号：US20070063266A1
公开(公告)日：2007-03-22
申请号：US11520698
申请日：2006-09-14
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/513
摘要： A semiconductor device includes a semiconductor region; a first high dielectric constant insulating film provided on the semiconductor region, the first high dielectric constant insulating film being a film other than alumina; a second high dielectric constant insulating film provided on the first high dielectric constant insulating film, the second high dielectric constant insulating film being an alumina film; and a conductive layer provided on the second high dielectric constant insulating film.
摘要翻译： 半导体器件包括半导体区域; 设置在所述半导体区域上的第一高介电常数绝缘膜，所述第一高介电常数绝缘膜是氧化铝以外的膜; 设置在第一高介电常数绝缘膜上的第二高介电常数绝缘膜，第二高介电常数绝缘膜是氧化铝膜; 以及设置在第二高介电常数绝缘膜上的导电层。
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