公开(公告)号：US11741014B2

公开(公告)日：2023-08-29

申请号：US17979472

申请日：2022-11-02

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit Singh Bains

IPC: G06F12/08 ,  G06F12/0875 ,  G06F9/448 ,  G06N3/02 ,  G06F3/06

CPC classification number: G06F12/0875 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0683 ,  G06F9/4498 ,  G06N3/02 ,  G06F2212/60

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US20230196065A1

公开(公告)日：2023-06-22

申请号：US18110162

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06N3/04 ,  G06F9/448 ,  G06F15/78 ,  G05B19/045 ,  G06N3/02

CPC classification number: G06N3/04 ,  G06F9/4498 ,  G06F15/7867 ,  G05B19/045 ,  G06N3/02

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

公开(公告)号：US10832760B2

公开(公告)日：2020-11-10

申请号：US16690598

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4076

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US20200285604A1

公开(公告)日：2020-09-10

申请号：US16884302

申请日：2020-05-27

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  G06F16/903 ,  H03K19/17728 ,  G06K9/00 ,  G06N5/00

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

公开(公告)号：US10733508B2

公开(公告)日：2020-08-04

申请号：US15871660

申请日：2018-01-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06N3/08 ,  G06K9/00 ,  G06N3/063

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

公开(公告)号：US10672441B2

公开(公告)日：2020-06-02

申请号：US16051202

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.

公开(公告)号：US20200090732A1

公开(公告)日：2020-03-19

申请号：US16690598

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C11/4093 ,  G11C7/10

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US20200089416A1

公开(公告)日：2020-03-19

申请号：US16694584

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F3/06 ,  G06N3/02 ,  G06F8/41

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US20200082856A1

公开(公告)日：2020-03-12

申请号：US16683018

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4074 ,  G06F13/18 ,  H04L25/03 ,  G11C11/4096 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4093 ,  G11C11/4076

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US10521366B2

公开(公告)日：2019-12-31

申请号：US16400739

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/10 ,  G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.