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    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    71.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220310641A1

    公开(公告)日：2022-09-29

    申请号：US17841925

    申请日：2022-06-16

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Nancy M. Lomeli

    IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    Microelectronic devices including staircase structures, and related memory devices and electronic systems
    72.
    发明授权
    Microelectronic devices including staircase structures, and related memory devices and electronic systems 有权

    公开(公告)号：US11424262B2

    公开(公告)日：2022-08-23

    申请号：US16821818

    申请日：2020-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Nancy M. Lomeli

    IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11556

    Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, a source tier underlying the stack structure, and a masking structure. The stack structure has tiers each comprising a conductive structure and an insulating structure. The stadium structure comprises a forward staircase structure, a reverse staircase structure, and a central region horizontally interposed between the forward staircase structure and the reverse staircase structure. The source tier comprises discrete conductive structures within horizontal boundaries of the central region of the stadium structure and horizontally separated from one another by dielectric material. The masking structure is confined within the horizontal boundaries of the central region of the stadium structure and is vertically interposed between the source tier and the stack structure. The masking structure comprises segments horizontally covering portions of the dielectric material horizontally interposed between the discrete conductive structures. Additional devices and electronic systems are also described.

    MICROELECTRONIC DEVICES WITH TIER STACKS WITH VARIED TIER THICKNESSES, AND RELATED METHODS AND SYSTEMS
    77.
    发明申请
    MICROELECTRONIC DEVICES WITH TIER STACKS WITH VARIED TIER THICKNESSES, AND RELATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20210398987A1

    公开(公告)日：2021-12-23

    申请号：US16904353

    申请日：2020-06-17

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Nancy M. Lomeli

    IPC: H01L27/115

    Abstract: Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    78.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210384208A1

    公开(公告)日：2021-12-09

    申请号：US16894519

    申请日：2020-06-05

    Applicant: Micron Technology, Inc

    Inventor： John D. Hopkins ,  Nancy M. Lomeli

    IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS
    80.
    发明申请
    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS 有权

    公开(公告)号：US20210265371A1

    公开(公告)日：2021-08-26

    申请号：US16799543

    申请日：2020-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Nancy M. Lomeli ,  Lifang Xu

    IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06

    Abstract: A microelectronic device comprises a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulating structures, a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers, conductive contact structures on the steps of the staircase structure, support pillar structures laterally offset in at least a first direction from the conductive contact structures and extending through the stack structure, and bridge structures comprising an electrically insulating material extending vertically through at least a portion of the stack structure and between at least some adjacent support pillar structures of the support pillar structures. Related memory devices, electronic systems, and methods are also described.

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